• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.84-92
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• 2002

As today's field programmable gate arrays have very large logic capacity as well as relatively fast operation speed, they're widely used in many application areas. However, debugging the design implemented in FPGA's is very time-consuming and painful as the internal signal probing usually requires large number of FPGA re-compilations, which take tremendously long time. In this paper, we analyze the problems in FPGA debugging and propose a new powerful debugging solution. With the proposed FPGA debugging solution, we can guarantee not only to provide 100% internal signal visibility without FPGA re-compilation for the design in FPGA's, but also to identify at least one design bug per FPGA compilation. An experimental result has clearly shown the proposed approach to FPGA debugging very powerful and practical.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.70-76
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• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1851-1857
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• 2009

In this paper, reuse module generation algorithm consider the power consumption for FPGA technology mapping is proposed. To proposed algorithm is RT library generating algorithm consider power consumption for reuse module using FPGA technology mapping. In the first, selected FPGA for power consumption calculation. Technology mapping process have minimum total power consumption consider LUT's constraint in selected FPGA. A circuit into device by selected proper modules of allocation result for power consumption constraint using data.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.25-29
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• 2008

The CORBA that supports FPGA has not been used generally and it is difficult to implement and to develop the CORBA for FPGA. In this paper we propose the way to design FPGA to support a CORBA component. For FPGA to support the CORBA component, embedded processor provided by FPGA and PCI based CORBA is utilized. The PCI based CORBA is for improving data transfer throughput. This paper will be organized as follows. In Chapter I, existing research trend and background are presented for why we propose design of FPGA that support the CORBA component. In Chapter II, FPGA design for supporting CORBA components is proposed and described in detail. In Chapter III, simple experiment is tested to confirm the proposed FPGA design. Finally session 4 is conclusion of this paper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2306-2310
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• 2007

In this paper, reuse module generation algorithm consider the power consumption for FPGA technology mapping is proposed. To proposed algorithm is RT library generating algorithm, consider power consumption for reuse module using FPGA technology mapping. In the first, selected FPGA for power consumption calculation. Technology mapping process have minimum total power consumption consider LUT's constraint in selected FPGA. A circuit into device by selected proper modules of allocation result for power consumption constraint using data.

• Journal of Practical Engineering Education
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• v.6 no.2
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• pp.91-97
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• 2014

Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.131-138
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• 2011

The previous FPGA cluster systems for a brute force search of DES keyspace have showed cost efficient performance, but the research on optimized implementation of the DES algorithm on a single FPGA has been insufficient. In this paper, the optimized DES implementation for a single FPGA of the commercial FPGA cluster system with 77 Xilinx Virtex5-LX50 FPGAs is proposed. Design space exploration using the number of pipeline stages in a DES core, the number of DES cores and the maximum clock frequency of a DES core is performed which leads to integrating 16 DES cores running at 333MHz. Also low power design is applied to reduce the loss of performance caused by limitation of power supply on each FPGA which results in fitting 8 DES cores running at 333MHz. When the proposed DES implementations would be used in the FPGA cluster system, it is estimated that the DES key would be found at most 2.03 days and 4.06 days respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.113-122
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• 2004

A new diagnosis method for FPGA interconnects is developed. The proposed method diagnoses all the fault types for FPGA interconnects. It is also applied to all the modem FPGA devices like Xilinx Virtex FPGAS. Most of all, it takes shorter time to diagnose all the faults than previous diagnosis methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.