• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.37-47
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• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• Transactions of the Korean Society of Automotive Engineers
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• v.25 no.1
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• pp.92-102
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• 2017

For an automotive surveillance radar system, fast-chirp train based FMCW (Frequency Modulated Continuous Wave) radar is a very effective method, because clutter and moving targets are easily separated in a 2D range-velocity map. However, pedestrians with low echo signals may be masked by strong clutter in actual field. To address this problem, we proposed in the previous work a clutter cancellation and moving target indication algorithm using the coherent phase method. In the present paper, we initially composed the test set-up using a 24 GHz FMCW transceiver and a real-time data logging board in order to verify this algorithm. Next, we created two indoor test environments consisting of moving human and stationary targets. It was found that pedestrians and strong clutter could be effectively separated when the proposed method is used. We also designed and implemented these algorithms in FPGA (Field Programmable Gate Array) in order to analyze the hardware and time complexities. The results demonstrated that the complexity overhead was nearly zero compared to when the typical method was used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1061-1068
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• 2017

A RVDT is a sensor that measures angular displacement and the output signal of RVDT is a DSBSC-AM signal. For this reason, a DSBSC-AM demodulation processor is required to determine the angular displacement from the output signal. In this paper, DADC(Digital Angle to DC) which extracts the angular displacement from the output signal of a RVDT is implemented based-on modified Costas Loop usually used in the demodulation of DSBSC-AM signal by using FPGA. DADC can used with both 4-wire and 5-wire RVDTs and can exactly compensate the phase difference between the input excitation and output signals of a RVDT unlike the conventional analog RVDT signal conditioners which require external components. Since digital signal processing technique that can enhance the linearity is exploited, DADC shows 0.035% linearity error, which is smaller than 0.005% that of a conventional analog signal conditioner. The DADC are tested in an integrated experimental environment which includes a commercial RVDT sensor, ADC and an analog output block.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.10 no.3
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• pp.237-242
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• 2016

The major advantage of slip-ring technology in Spiral CT is that it facilitates continuous rotation of the x-ray tube, so that volume data can be acquired from a patient quickly. Not only for such a fast scan, but also for the dose reduction purpose, high signal-to-noise ratio and fast data acquisition system is required. In this study, we have built a multi-channel photodetector and multi-channel data acquisition system for CT application. The detector module consisted of CdWO4 crystal and Si photodiode in 16 channels. For the performance test of the preamplifier stage, both the transimpedance and switched integrator types are optimized for the photodetector modules. Switched integrator showed better noise performance in the limited bandwidth which is suitable for the current CT application. The control sequence for data acquisition and 20 bit ADC is designed with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and implemented on FPGA(Field Programmable Gate Array) chip. Our Si photodiode detector module coupled to CdWO4 crystal showed comparable signal with other commercially available photodiode for CT. Switched integrator type showed higher SNR but narrower bandwidth compared to transimpedance preamplifier. Digital hardware is designed by FPGA, so that the control signal could be redesigned without hardware alteration.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.2018-2030
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• 2015

A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

• Smart Structures and Systems
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• v.11 no.3
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• pp.261-282
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• 2013

Structural health monitoring (SHM) is an application area of Wireless Sensor Networks (WSNs) which usually needs high data communication rate to transfer a large amount of monitoring data. Traditional sink node can only process data from one communication channel at the same time because of the single radio chip structure. The sink node constitutes a bottleneck for constructing a high data rate SHM application giving rise to a long data transfer time. Multi-channel communication has been proved to be an efficient method to improve the data throughput by enabling parallel transmissions among different frequency channels. This paper proposes an 8-radio integrated sink node design method based on Field Programmable Gate Array (FPGA) and the time synchronization mechanism for the multi-channel network based on the proposed sink node. Three experiments have been performed to evaluate the data transfer ability of the developed multi-radio sink node and the performance of the time synchronization mechanism. A high data throughput of 1020Kbps of the developed sink node has been proved by experiments using IEEE.805.15.4.

• Journal of Advanced Navigation Technology
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• v.20 no.5
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• pp.453-461
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• 2016

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. Therefore, advanced ZigBee (AZB) systems that support the various data rate under 250 kbps are proposed. However, the preamble structure for AZB systems causes the complexity increase of time synchronization circuits. In this paper, we propose preamble structure and time synchronization algorithm which can solve the problem of the complexity increase of time synchronization circuits. Implementation results show that the proposed time synchronizer for AZB systems include the logic slices of 6.92 k and, which are reduced at the rate of 62.3% compared with existing architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.639-644
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• 2011

By the development of the information superhighway, the current data communication system can be exchanged data quickly and precisely between subscribers. In this paper, LVTTL(Low Voltage Transistor Transistor Logic), Using the fundamental one logic at several kinds of used in communication systems, the LVTTL transmission characteristics were measured by according to the change data transfer rate and the transmission line length. Because the transmission line length required on the current system is 30cm, We analysed LVTTL data transfer characteristics according to the transmission line length required on the current system. The amplitude level of LVTTL at 10Mbps is 3V and 50Mbps is 2.2V and 100Mbps is 2V and 125Mbps is 1.5V and 150Mbps is 1.4V. The length of transmission line 30cm was stable state up to 100Mbps data transfer rate.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.12
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• pp.136-144
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• 2021

The purpose of this study was to develop and verify a precision transmission error measurement system for a gear pair. The transmission error measurement system of the gear pair was developed as a measurement unit, signal processing unit, and signal analysis unit. The angular displacement for calculating the transmission error of the gear pair was measured using an encoder. The signal amplification, interpolation, and transmission error calculation of the measured angular displacement were conducted using a field-programmable gate array (FPGA) and a real-time processor. A high-pass filter (HPF) was applied to the calculated transmission error from the real-time processor. The transmission error measurement test was conducted using a gearbox, including the master gear pair. The same test was repeated three times in the clockwise and counterclockwise directions, respectively, according to the load conditions (0 - 200 N·m). The results of the gear transmission error tests showed similar tendencies, thereby confirming the stability of the system. The measured transmission error was verified by comparing it with the transmission error analyzed using commercial software. The verification showed a slight difference in the transmission error between the methods. In a future study, the measurement and analysis method of the developed precision transmission error measurement system in this study may possibly be used for gear design.