• Journal of Korean Society of Transportation
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• v.22 no.5
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• pp.123-137
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• 2004

The study on traffic assignment is actively being performed which reflect networks status using time. Its background is increasing social needs to use traffic assignment models in not only hardware area of road network plan but also software area of traffic management or control. In addition, multi-class traffic assignment model is receiving study in order to fill a gap between theory and practice of traffic assignment model. This model is made up of two, one of which is multi-driver class and the other multi-vehicle class. The latter is the more realistic because it can be combined with dynamic model. On this background, this study is to build multidynamic model combining the above-mentioned two areas. This has been a theoretic pillar of ITS in which dynamic user equilibrium assignment model is now made an issue, therefore more realistic dynamic model is expected to be built by combining it with multi-class model. In case of multi-vehicle, FIFO would be violated which is necessary to build the dynamic assignment model. This means that it is impossible to build multi-vehicle dynamic model with the existing dynamic assignment modelling method built under the conditions of FIFO. This study builds dynamic network model which could relieve the FIFO conditions. At the same time, simulation method, one of the existing network loading method, is modified to be applied to this study. Also, as a solution(algorithm) area, time dependent shortest path algorithm which has been modified from existing shortest path algorithm and the existing MSA modified algorithm are built. The convergence of the algorithm is examined which is built by calculating dynamic user equilibrium solution adopting the model and algorithm and grid network.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.18-27
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• 2010

This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2B
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• pp.1-10
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• 2005

TCP/IP protocols have been implemented in software program running on CPU in end systems. As the increased demand of fast protocol processing, it is required to implement the protocols in hardware, and Host Interface is responsible for communication between external CPU and the hardware blocks of TCP/IP implementation. The Host Interface follows AMBA AHB specification for the communication with external world. For control flow, the Host Interface behaves as a slave of AMBA AHB. Using internal Command/status Registers, the Host Interface receives commands from CPU and transfers hardware status and header information to CPU. On the other hand, the Host Interface behaves as a master for data flow. Data flow has two directions, Receive Flow and Transmit Flow. In Receive Flow, using internal RxFIFO, the Host Interface reads data from UDP FIFO or TCP buffer and transfers data to external RAM for CPU to read. For Transmit Flow, the Host Interface reads data from external RAM and transfers data to UDP buffer or TCP buffer through internal TxFIFO. TCP/IP hardware blocks generate packets using the data and transmit. Buffer Descriptor is one of the Command/Status Registers, and the information stored in Buffer Descriptor is used for external RAM access. Several testcases are designed to verify TCP/IP functions. The Host Interface is synthesized using the 0.18 micron technology, and it results in 173 K gates including the Command/status Registers and internal FIFOs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.727-735
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• 2001

본 논문은 8-VSB Advanced Digital TV용으로 사용할 수 있도록 ATSC(Advanced Television Standard Committee)의 규약을 만족시키도록 구현한 Reed Solomon 디코더에 대하여 기술한다. 구현된 RS Decoder는 공유된 Tree 구조의 Arithmetic 블록을 사용하여 종래의 기술보다 더 효율적인 연산기 구조를 제안하였으며 빠른 에러 탐지와 정정 시간으로 인한 FIFO의 사용갯수와 Latency Time을 크게 감소시킨 개선된 구조를 제안한다. 일반적으로 2N+A만큼의 Latency Time과 FIFO 개수를 N+A 만큼으로 감소시켰다. 이 RS 디코더는 Verilog HDL로 설계되었고 Synopsys Design Compiler에 의해 합성되었다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.931-933
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• 2004

In a SoC environment, asynchronous design techniques offer solutions for problems of synchronous design techniques. Asynchronous FIFOs have the advantages of easier interconnection methods and higher throughput than synchronous ones. Low latency and high throughput are two imp ortant standards in asynchronous FIFOs. We present low latency asynchronous FIFO in the paper, which optimizes GasP[6]. Pre-layout of HSPICE simulations of a 8-stage FIFO on 1-bit datapath using Anam's 0.25$\mu\textrm{m}$ technology indicates 17% lower latency than GasP.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.9
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• pp.12-19
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• 2002

Guaranteed Frame Rate(GFR) service is intended to efficiently support TCP/IP traffic in ATM networks. The GFR service not only guarantees a minimum service rate at the frame level, but also supports a fair share of available bandwidth. The original GFR proposal outlined two switch implementation scheme : FIFO Queuing and perVC-Queuing. In general, it has been shown that FIFO Queuing is not sufficient to provide rate guarantees and perVC-Queuing with scheduling is needed. In perVC-Queuing implementation, scheduling algorithm plays key rule to provide rate guarantees and to improve fairness. We proposed a new scheduling algorithm for the GFR service. Proposed algorithm can provide minimum service rate guarantee and fair sharing to GFR VCs. Computer simulation results show that proposed scheduling scheme provide a much better performance in TCP Goodput and fairness than previous scheme.

• Journal of Internet Computing and Services
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• v.1 no.2
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• pp.61-67
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• 2000

In case of the remote controllable web-camera that was took notice especially in internet real-time broadcasting systems, a great many clients connect the server of web-camera to request the service. So, the scheduling methods are important. Web-camera systems have used to the traditional FIFO(First In First Out) or SDF(Shortest Distance First) scheduling method. But they does not satisfy both the minimization of moving distance on the web-camera and the fairness on the users. In this paper, We propose the 2D scheduling method, As a result, the moving distance of the web-camera decreases compared with FIFO scheduling method. And the starvation state on the user's request does not happen compared with SDF scheduling method. Thus, if the remote controllable web-camera systems use the 2D scheduling method, they are satisfied with the minimization of moving distance on the remote controllable web-camera and the fairness on the users simultaneously. Therefore the user's satisfaction and the performance of the systems are improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1985-1992
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• 2011

PE(Passive Entry) is an automotive technology which allows a driver to lock and unlock door of vehicle without using smart key buttons personally. PG(Pssive Go) is an automotive technology which offers the ability to start and stop the engine when there is a driver in vehicle with smart key. When these two functions are unified, we call it PEG(Passive Entry/Go). LF(Low Frequency) antenna driver which is one of core technologies in PEG is composed of a digital part which processes commands and an analog part which generates sine waveform. The digital part of antenna driver receives commands from MCU(or ECU), and processes requested commands by MCU, and stores antenna-related driver commands and data on an internal FIFO block. The digital part takes corresponding actions for commands read from FIFO and then transfers modulated LF data to analog part. The analog part generates sine waveform and transmits outside through antenna. The designed digital part for LF antenna driver can acomplish faster LF data transmission than that of conventional product. LF antenna driver can be applicable to the areas such as PEG for automotive and gate opening and closing of building.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.