• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.617-620
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• 2002

본 논문에서는 single bank와 multi bank FIFO를 지원하는 CMOS FIFO memory compiler를 개발 검증하였다. 이 컴파일러를 사용해서 설계자는 구현하고자 하는 어플리케이션에 적합한 high speed, high density, low power를 갖는 on-chip memory를 빠른 시간에 만들어 낼 수 있으므로 설계 시간을 절약할 수 있다. 이와 더불어 설계된 FIFO 의 시뮬레이션을 지원하기위한 Verilog 시뮬레이션 모델을 제공하였다. 현재 FIFO를 구성하는 단위 셀들은 0.6um 3-metal 공정을 이용하여 설계하였으며 공정의 변화에 따라 대상 공정에 맞도록 단지 몇 개의 단위 셀만을 재 설계하고 그에 대한 정보를 갱신해줌으로써 공정의 변화에 대처 할 수 있도록 하였다. 설계된 컴파일러를 이용해 생성된 FIFO 는 표준 셀 라이브러리를 이용한 합성 가능한 FIFO에 대하여 $16bit{\times}16word$ FIFO에서 면적면에서 93%, 속도면에서 70%의 향상을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.117-124
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• 1998

As window sized increases, the throughput input-buffered packet switch with a window scheme improves on random traffic condition. However, the improvement diminishes quickly under bursty traffic. In this paper, we propose Burst Head Addressable FIFO mechanism and memory structure having search capability in unit of burst header to compensate the sensitiveness of the windowed scheme to bursty traffic. The performance of a input-buffered switch using the proposed Burst Header Addressable FIFO input buffer was analyzed using computer simulations. The maximum throughput of the conventional FIFO scheme approaches an asymptotic value 0.5 as mean burst length increases. The maximum throughput of the proposed scheme is greater than that of the conventional scheme for any mean burst length and window size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.647-650
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• 2004

MAC RX FIFO은 10Gbps전용 전송속도에서 제공하는 FIFO모듈이다. 10Gbps이상의 전송속도에서는 전송부, 수신부모두 양방향 전송신가능한 Full Duplex(전이중)방식을 사용한다. 기존 FIFO의 임시 버퍼기능 뿐만 아니라 프레임 흐름 컨트롤 블록을 적용하여 전송간의 프레임 흐름제어 기능을 수행한다. 하위계층에서 MAC으로부터 전송되는 데이터는 64비트와 데이터 유효 정보를 가진 8비트 데이터 유효 정보비트를 가진다. 이렇게 전송되는 데이터는 MAC RX FIFO에 프레임단위로 저장되어 프레임간의 구분정보 Codeword프레임을 확인하여 새프레임 데이터를 확인한다. 사용자계층에는 데이터 128비트와 유효 정보비트 16비트로 사용자계층에 전송한다. 본 논문에서는 10G 전송속도을 갖는 MAC RX FIFO을 설계한다. VHDL언어를 사용하였고 ModelSim5.6a로 시뮬레이션하여 파형분석과 타이밍 분석하여 정상적인 동작을 확인한다. MAC RX FIFO는 10Gbps전송속도에서 요구되어지는 모듈에서 Flow Control, Pause프레임기능을 갖는 모듈에 적용되어 사용가능 할 것으로 사료된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.259-266
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• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of Internet Computing and Services
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• v.6 no.2
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• pp.49-57
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• 2005

Connector's role between components is very important in the CBD(Component Based Development). The most connector has process ADL based rrethod was choosing FIFO method by component request. But in case many component's with various characteristics request It is difficult that this method operate efficiently, In this research, I did design and implement priority connector considering component's processing time, Also, I used Wright architecture for formal specification. Application result of proposed connector was spend more 388ms compares with existent FIFO method in total processing time. But this method could handle preferentially from components that have short processing time. Also, in case of component's waiting time in connector, existent FIFO method is 23323,1 ms and proposal method is 12731.27ms, So, proposal method could reduce waiting time for component process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1238-1244
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• 2001

Earlier efforts on optical access concentrated on the design of PONs for the collection and distribution portion of the access network. In these networks the optical hardware in the RN is very simple, but a multiple access protocol is needed for upstream traffic control. On the other hand, the role of communications is already well established in the office environment. With the advent of cheap, affordable broadband communications and the increasing complexity of consumer electronics, it seems natural to extend the network into the home. As the application of Home Area Network is ever increasing, we therefore consider connectivity between access network and home network which generates various traffic to design MAC protocol over residential network. Global-FIFO is quite simple and allows dynamic upstream bandwidth assignment on the basis of a request-and-permit mechanism. It has good bandwidth efficiency and being cell-based, it does not consider the various traffic from home network. In this paper, we design and analyze the new MAC resource assignment algorithm called MQ-FIFO (Multiple Queue-FIFO) that provides good performance under the environment of ATM-PON and Home Network.

• The KIPS Transactions:PartC
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• v.15C no.4
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• pp.321-328
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• 2008

In this paper, we analyze web response time depending on queue managements and transmission latencies in highly congested network situation. Under FIFO scheme, the response times are for three different sizes of queue are almost the same, but the response time increases as traffic intensity increases. The performance between different queue sizes shows more different in 90% and 98% traffic intensity than in 80% traffic intensity. Especially the difference becomes bigger in short latency case than long latency case. Under RED scheme, three differently tunned RED schemes do not impact on the response time when the size of queue is relatively large. When the queue size becomes smaller, the response time of the differently tunned RED schemes becomes different for short latency case while the response times are almost same for long latency case. When comparing FIFO and RED schemes under same size of queue, RED scheme shows less response time than that of FIFO for the long latency case in high traffic intensity.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.637-639
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• 2004

GFR 서비스는 ATM 네트워크에서 인터넷 트래픽을 효과적으로 처리하기 위하여 ATM 포럼에서 정의되었다. 단순 FIFO 기반 GFR 구현 기법은 가상 연결 단위의 계수기나 분리된 버퍼 관리가 필요치 않아 실용적이지만, QoS가 만족스럽지 않다. 본 논문은 이 구현 기법의 QoS를 개선할 수 있는 방안을 찾기 위해, 이 구현 기법의 문제점을 명확히 하고자 컴퓨터 시뮬레이션을 수행하고 그 결과를 분석하였다. TCP 트래픽에 따른 성능 평가를 위해 Tahoe와 New-Reno 두 버전을 각각 적응하였다.