• Journal of the Korean Society for Nondestructive Testing
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• v.13 no.2
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• pp.20-30
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• 1993

Electric Speckle Pattern Interferometry (ESPI) using a CW-laser, a video system and an image processor was applied to the thermal coefficient measurements on free thermal expansions at high temperatures : ESPI provides the distribution of in-plane displacement resolved in a preselected direction. ESPI retains the merits of little or no surface preparation, no contact with the surface and the real-time presentation of interference fringes. Appling ESPI at high temperatures, several problem which caused the reduction of fringe visibility were encountered. The problem on the turbulence in the hot air surrounding high temperature objects will be solved by using a vacuum chamber. The background radiations from the objects were suppressed considerably by an interference filter. The problem on the oxidation of the object surface could't be solved. The interference fringe, whose spacings were calculated by FFT to avoid human error, were observable up to $800^{\circ}C$. The results measured by ESPI were nearly equal to the data which have already been published, up to about $800^{\circ}C$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8A
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• pp.583-591
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• 2009

OFDM(orthogonal frequency division multiplexing) signal with high PAPR(peak to average power ratio) produces the nonlinear distortion and/or decreases down the power efficiency of HPA(high power amplifier). So, the IMD(inter-modulation distortion) reduction method was proposed to reduce the nonlinear distortion, which shows better BER(bit error rate) performance than the PAPR reduction methods. However, IMD reduction method has inherent problem which system complexity and processing time increases because the FFT(fast Fourier transform) processor is added in transmitter and decision criterion of IMD reduction method is computed in frequency domain,. In this paper, therefore, we propose a new IMD reduction method to reduce the computational complexity and structure of IMD computation. And we apply this proposed method into OFDM system using PTS(partial transmit sequence) scheme and compare the computational complexity between conventional and proposed IMD reduction method. This method can reduce the system size and computational complexity. Also, the proposed has almost same BER performance with the conventional IMD reduction method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.10
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• pp.1172-1180
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• 2007

OFDM system has very good high spectral efficiency and the robustness to the frequency-selective fading. Because of the high PAPR, OFDM signals can be distorted in nonlinear HPA(High Power Amplifier). So, to overcome the nonlinear distortion, it is very important to reduce the IMD value. With respect to the BER performance, IMD reduction method is better than the PAPR reduction method. However, IMD reduction method has much more system complexity because of the additional FFT processor in transmitter. In this paper, we study the OFDM communication system based on the IMD reduction method using SPW method. A new IMD reduction method is proposed to reduce the computational complexity. SPW method is to divide the input OFDM data into several sub-blocks and to multiply phase weighting values with each sub-blocks for the reduction of PAPR or IMD. Unlike the conventional method, the system size and computational complexity can be reduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9A
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• pp.931-939
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• 2007

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.161-161
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• 2017

스마트 시설환경의 제어 요소는 난방기, 창 개폐, 수분/양액 밸브 개폐, 환풍기, 제습기 등 직접적으로 시설환경의 조절에 관여하는 인자와 정보 교환을 위한 통신, 사용자 인터페이스 등 간접적으로 제어에 관련된 요소들이 복합적으로 존재한다. PID 제어와 같이 하는 수학적 논리를 바탕으로 한 제어와 전문 관리자의 지식을 기반으로 한 비선형 학습 모델에 의한 제어 등이 공존할 수 있다. 이러한 다양한 요소들을 복합적으로 연동시키기 위해선 기존의 시퀀스 기반 제어 방식에는 한계가 있을 수 있다. 관행의 방식과 같이 시계열 상에서 획득한 충분한 데이터를 이용하여 제어의 양과 시점을 결정하는 방식은 예외 상황에 충분히 대처하기 어려운 단점이 있을 수 있다. 이러한 예외 상황은 자연적인 조건의 변화에 따라 불가피하게 발생하는 경우와 시스템의 오류에 기인하는 경우로 나뉠 수 있다. 본 연구에서는 실시간으로 변하는 시설환경 내의 다양한 환경요소를 실시간으로 분석하고 상응하는 제어를 수행하여 수학적이며 예측 가능한 논리에 의해 준비된 제어시스템을 보완할 방법을 연구하였다. 과거의 고성능 컴퓨팅(HPC; High Performance Computing)은 다수의 컴퓨터를 고속 네트워크로 연동하여 집적적으로 연산능력을 향상시킨 기술로 비용과 규모의 측면에서 많은 투자를 필요로 하는 첨단 고급 기술이었다. 핸드폰과 모바일 장비의 발달로 인해 소형 마이크로프로세서가 발달하여 근래 2 Ghz의 클럭 속도에 이르는 어플리케이션 프로세서(AP: Application Processor)가 등장하기도 하였다. 상대적으로 낮은 성능에도 불구하고 저전력 소모와 플랫폼의 소형화를 장점으로 한 AP를 시설환경의 실시간 제어에 응용하기 위한 방안을 연구하였다. CPU의 클럭, 메모리의 양, 코어의 수량을 다음과 같이 달리한 3가지 시스템을 비교하여 AP를 이용한 마이크로 클러스터링 기술의 성능을 비교하였다.1) 1.5 Ghz, 8 Processors, 32 Cores, 1GByte/Processor, 32Bit Linux(ARMv71). 2) 2.0 Ghz, 4 Processors, 32 Cores, 2GByte/Processor, 32Bit Linux(ARMv71). 3) 1.5 Ghz, 8 Processors, 32 Cores, 2GByte/Processor, 64Bit Linux(Arch64). 병렬 컴퓨팅을 위한 개발 라이브러리로 MPICH(www.mpich.org)와 Open-MP(www.openmp.org)를 이용하였다. 2,500,000,000에 이르는 정수 중 소수를 구하는 연산에 소요된 시간은 1)17초, 2)13초, 3)3초 이었으며, $12800{\times}12800$ 크기의 행렬에 대한 2차원 FFT 연산 소요시간은 각각 1)10초, 2)8초, 3)2초 이었다. 3번 경우는 클럭속도가 3Gh에 이르는 상용 데스크탑의 연산 속도보다 빠르다고 평가할 수 있다. 라이브러리의 따른 결과는 근사적으로 동일하였다. 선행 연구에서 획득한 3차원 계측 데이터를 1초 단위로 3차원 선형 보간법을 수행한 경우 코어의 수를 4개 이하로 한 경우 근소한 차이로 동일한 결과를 보였으나, 코어의 수를 8개 이상으로 한 경우 앞선 결과와 유사한 경향을 보였다. 현장 보급 가능성, 구축비용 및 전력 소모 등을 종합적으로 고려한 AP 활용 마이크로 클러스터링 기술을 지속적으로 연구할 것이다.

• International Journal of Control, Automation, and Systems
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• v.4 no.6
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• pp.763-768
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• 2006

The two-for-one(TFO) twister is precision machinery that twists fibers rapidly under constant tension. Since the quality of the twisted yarn is directly deteriorated by faults of the twister, such as the distortion of the spinning axis, bearing abrasion, and tension irregularity, it is important to detect faults of the TFO twister at an early stage. In this research, a new algorithm is proposed to detect faults of the TFO twister and their causes, by measuring the vibrations of the TFO twister and obtaining frequency components with a FFT algorithm. The TFO twister with faults showed increased vibrations and each fault generated vibrations at different frequencies. By analyzing changes of characteristics of vibrations, we can determine faulty twisters. The proposed fault detection algorithm can be implemented cheaply with a signal processor chip. It can be used to find when to repair a faulty TFO twister without much loss of yam on-line.

• Journal of the Optical Society of Korea
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• v.19 no.4
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• pp.334-339
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• 2015

Terabit-per-second (Tb/s) transmission capacity for the next generation of long-haul communication networks can be achieved using multicarrier optical super-channel technology. In an elastic orthogonal frequency division multiplexing (OFDM) super-channel transmission system, demultiplexing a portion of an entire spectrum in the form of a subband with minimum power is critically required. A major obstacle to achieving this goal is the analog-to-digital converter (ADC), which is power-hungry and extremely expensive. Without a proper ADC that can work with low power, it is unrealistic to design a 100G coherent receiver suitable for a commercially deployable optical network. Discrete Fourier transform (DFT) is often seen as a primary technique for understanding partial demultiplexing, which can be attained either optically or electronically. If fairly comparable performance can be achieved with an all-optical DFT circuit, then a solution independent of data rate and modulation format can be obtained. In this paper, we investigate two distinct OFDM super-channel receiver models, based on electronic and all-optical DFT-technologies, for partial carrier demultiplexing in a multi-Tb/s transmission system. The performance comparison of the receivers is discussed in terms of bit-error-rate (BER) performance.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.35-42
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• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.453-456
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• 2001

21세기에 새로운 분야로 대두되고 있는 가상현실은 많은 사람들의 흥미를 끌고 있다. 상상 속에서나 가능하던 일들을 현실감과 입체감을 통해 실제처럼 느낄 수 있게 해준다는 것이 가상현실의 가장 큰 매력일 것이다. 가상현실을 요하는 멀티미디어 기기들의 활발한 시장진출로 3D 효과를 가진 오디오/비디오의 하드웨어 구현이 불가피하다. 본 연구에서는 휴대용 기기들에서 실시간 3D 입체음향 효과를 얻을 수 있도록 하드웨어를 구성하였다. 기존의 입체음향 기술에서 사용되는 콘볼루션 방법은 계산량이 많기 때문에 실시간 구현이 어렵다. 그러나 제안된 방식은 FFT를 사용하여 주파수 영역에서 처리함으로써 계산량을 줄여 하나의 프로세서로도 실시간 처리가 가능하도록 하였다. 저가/저전력/소형화조건을 요구하는 휴대용 기기에서 3D 입체 음향 효과를 얻을 수 있는 것이다. DSP는 TI(Texas Instruments)사의 16비트 고정소수점(fixed-point) 프로세서인 TMS320C5416을 사용한다. 구현된 3D 입체음향 칩은 입체음향을 필요로 하는 휴대용 MP3 Player, 가전용 오디오/비디오 등에 응용될 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1713-1719
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• 2022

As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms.