• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.60-64
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• 2007

In this paper, we designed FFT for European DTV and implemented system with Stratix EP1S25F672C6 FPGA At the implemented FFT, we used SIC architecture. SIC architecture is composed of algorithm-specific processing element, RAM memory, registers, and a central or distributed control unit. Designed FFT was acceptable either 2K or 8K point FFT processing, and is selectable guard interval such as 1/4, 1/8, 1/16, 1/32. Consequently, it was suitable for the standard of DVB-T(Digital Terrestrial Video Transmission System) specification. It resulted in 12% of total logic gate and 53% of total memory bit in Stratix device.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.469-472
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• 2007

최근 많은 광대역 유무선 통신 응용분야에서 OFDM(Orthogonal Frequency Division Multiplexing) 방식을 표준기술로 채택하고 있다 OFDM 방식의 고속 무선 데이터 통신를 위한 FFT 프로세서는 일반적으로 DSP(Digital Signal Processing)로 구현되었으나, 큰 전력 소비를 필요로 한다. OFDM의 단점인 전력문제를 보안하기 위해서 Current-mode FFT LSI가 제안되었다. 본 논문에서는 Current-mode FFT LSI의 구현을 위한 저전력 IVC를 설계하였다. 설계된 IVC는 FFT Block의 출력이 $13.65{\mu}A$ 이상일 때에 3V 이상의 전압을 출력하고, FFT Block의 출력이 $0.15{\mu}A$ 이하일 때에 0.5V 이하의 전압을 출력한다. 그리고 IVC의 총 소모전력은 약 1.65mW이다. $0.35{\mu}A$ 공정에서의 저전력 IVC를 설계함으로서, $0.35{\mu}A$ 공정에서의 Current-mode FFT LSI의 설계가 가능해졌다. 저전력 OFDM 통신용 Current-mode FFT LSI는 무선통신의 발전에 기여할 것으로 전망한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1623-1626
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• 2002

본 논문에서는 IEEE 802.11a 무선 랜 모뎀에 적용할 파이프 라인구조의 FFT 설계 및 구현에 대해서 제시한다. 구현된 FFT의 기본 구조는 radix-4 Single Delay Format 이나 제안된 나비 연산기에 의해서 복잡도는 radix-2방식과 동일하며 저전력을 고려해서 구현하였다. 구현된 FFT는 $0.35{\mu}m$ LG 라이브러리를 이용하여 합성되었고 64-포인트 FFT/IFFT를 $4{\mu}s$에 수행을 하며 16MHz로 동작을 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.26 no.1
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• pp.101-108
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• 1990

The processing efficiency of the special purpose hardware which is designed and implemented for the FFT caculation was investigated in this paper. This hardware equipment was consisted of LSI chips of four high speed multiplier and adde $r_stractor, and was interfaced with the 16bit microcomputer(NEC PC-9801E). The FFT processing time by this hardware equipment was improved approximately 4.8 times by the co-processor(Intel C8087-3).3).

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1365-1368
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• 2002

OFDM은 제4세대 변조기술로 일컬어지는 방식이다. 이는 최근 유럽에서 디지털 오디오 방송(DAB)과 디지털 비디오 방송(DVB)에 표준이 되었으며, IEEE 802.11a 무선 LAN 에서도 이 방식을 채택했고, ADSL, VDSL 등에서도 사용되어지고 있다. 본 논문에서는 이러한 OFDM 방식의 핵심이라고 할 수 있는 64포인트 FFT(Fast Fourier Transform)하드웨어 프로세서의 여러 가지의 구현된 예를 비교 분석하고, 가장 효율적인 방법인 Radix-2 SDF(Singlepath Delay Feedback)[1] 방법을 개선하여 새로운 구조를 제안하였다. 동일한 속도 성능을 가지는 여러구조 중에서 적은 수의 지연소자를 활용하여 FFT 크기를 작게 한 것이 SDF 방식으로 가장 널리 사용되고 있다. 본 논문에서는 SDF 방식이 내부적으로 4개의 복소곱셈기를 필요로 하는데 비해 2개의 복소곱셈기만을 사용하는 구조로 변형하고 컨트롤을 조절하여 새로운 구조를 설계하였다. 구현한 결과, FFT에서 전체 구조의 약 80%를 차지하는 복소곱셈기의 수를 절반으로 줄여 FFT 하드웨어 크기를 SDF 방식의 60% 정도로 줄일 수 있게 되었고, 이러한 구현방식은 64포인트 FFT만이 아닌 더 큰 크기의 FFT를 구현함에 있어서도 동일하게 적용할 수 있으며 현재 국내외에 발표된 논문 중 성능 대 면적비가 가장 우수한 구조이다.

• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.204-214
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• 2013

Recently various research have been conducted relating to the implementation of signal processing or communication system by software using the massively parallel processing capability of the GPU. In this work, we focus on reducing software simulation time of 2K/8K FFT in DVB-T by using GPU. we estimate the processing time of the DVB-T system, which is one of the standards for DTV transmission, by CPU. Then we implement the FFT processing by the software using the NVIDIA's massively parallel GPU processor. In this paper we apply stream process method to reduce the overhead for data transfer between CPU and GPU, coalescing method to reduce the global memory access time and data structure design method to maximize the shared memory usage. The results show that our proposed method is approximately 20~30 times as fast as the CPU based FFT processor, and approximately 1.8 times as fast as the CUFFT library (version 2.1) which is provided by the NVIDIA when applied to the DVB-T 2K/8K mode FFT.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.23-25
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• 2023

본 논문에서는 FPGA 를 활용하여 radix-2 Fast Fourier Transform(FFT) 알고리즘을 빠르고 효율적으로 구현하는 연구에 대해 기술한다. 본 논문에서 zybo z7-20 FPGA 를 사용하여 Processing System(PS)에서만 동작하는 구현과 Programmable Logic(PL)에서 동작하며 파이프라인과 병렬처리를 사용한 FFT 구현 결과를 비교한다. 또한 유사한 논문과의 결과 비교를 통해 본 구현 방법의 연산 시간 및 리소스 사용의 효율성을 분석한다.