• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.304-310
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• 2017

In this paper, we propose the architecture of an IPM based lane detector for autonomous vehicles to detect and control the driving route along the curved lane. In the IPM image, we divide the area into two fields, Far/Near Field, and the lane candidate region is detected using the Hough transform to perform the matching for the curved lane. In autonomous vehicles, various algorithms must be embedded in the system. To reduce the system resources, we proposed a method to minimize the number of memory accesses to the image and various parameters on the external memory. The proposed circuit has 96% lane recognition rate and occupies 16% LUT, 5.9% FF and 29% BRAM in Xilinx XC7Z020. It processes Full-HD image at a rate of 42 fps at a 100 MHz operating clock.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.605-619
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• 2003

The main memory DBMS(MMDBMS) efficiently supports various database applications that require high performance since it employs main memory rather than disk as a primary storage. In this paper, we discuss the index manager of the Tachyon, a next-generation MMDBMS. Recently, the gap between the CPU processing and main memory access times is becoming much wider due to rapid advance of CPU technology. By devising data structures and algorithms that utilize the behavior of the cache in CPU, we are able to enhance the overall performance of MMDBMSs considerably. In this paper, we address the practical implementation issues and our solutions for them obtained in developing the cache-conscious index manager of the Tachyon. The main issues touched are (1) consideration of the cache behavior, (2) compact representation of the index entry and the index node, (3) support of variable-length keys, (4) support of multiple-attribute keys, (5) support of duplicated keys, (6) definition of the system catalog for indexes, (7) definition of external APIs, (8) concurrency control, and (9) backup and recovery. We also show the effectiveness of our approach through extensive experiments.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.509-516
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• 2001

As results of many genome projects, genomic sequences of many organisms are revealed. Various methods such as global alignment, local alignment are used to analyze the sequences of the organisms, and k -mer analysis is one of the methods for analyzing the genomic sequences. The k -mer analysis explores the frequencies of all k-mers or the symmetry of them where the k -mer is the sequenced base with the length of k. However, existing on-memory algorithms are not applicable to the k -mer analysis because a whole genomic sequence is usually a large text. Therefore, efficient data structures and algorithms are needed. String B-tree is a good data structure that supports external memory and fits into pattern matching. In this paper, we improve the string B-tree in order to efficiently apply the data structure to k -mer analysis, and the results of k -mer analysis for C. elegans and other 30 genomic sequences are shown. We present a visualization system which enables users to investigate the distribution and symmetry of the frequencies of all k -mers using CGR (Chaotic Game Representation). We also describe the method to find the signature which is the part of the sequence that is similar to the whole genomic sequence.

• The Journal of the Acoustical Society of Korea
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• v.20 no.4
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• pp.22-28
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• 2001

This paper describes the implementation of a robust speaker position location system using the voice signal received by microphone array. To be robust to the reverberation which is the major factor of the performance degradation, low-frequency phase restoration algorithm which eliminates the influence of reverberations using the low-frequency information of the CPSP function is proposed. The implemented real-time system consists of a general purpose DSP (TMS320C31 of Texas instruments), analog part which contains amplifiers and filters, and digital part which is composed of the external memory and 12-bit A/D converter. In the real conference room environment, the implemented system that was constructed by the proposed algorithms showed better performance than the conventional system. The error of the TDOA estimation reduced more than 15 samples.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.486-497
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• 2001

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image-processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. The proposed two-dimensional addressing mode for image processor has the following advantages. The proposed instruction combines several instructions to load a pixel data from an external memory to a register. Hence, the proposed instruction reduces required code size so that it satisfies high performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer The proposed two-dimensional addressing mode is applicable to DSP, media processor, graphic device, and so on. In this paper, we propose a new concept of two-dimensional addressing mode and an efficient hardware implementation method of it.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.387-398
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• 2002

As whole genome sequences of many organisms have been revealed by small-scale genome projects, the intensive research on individual genes and their functions has been performed. However on-memory algorithms are inefficient to analysis of whole genome sequences, since the size of individual whole genome is from several million base pairs to hundreds billion base pairs. In order to effectively manipulate the huge sequence data, it is necessary to use the indexed data structure for external memory. In this paper, we introduce a workbench system for analysis and visualization of whole genome sequence using string B-tree that is suitable for analysis of huge data. This system consists of two parts : analysis query part and visualization part. Query system supports various transactions such as sequence search, k-occurrence, and k-mer analysis. Visualization system helps biological scientist to easily understand whole structure and specificity by many kinds of visualization such as whole genome sequence, annotation, CGR (Chaos Game Representation), k-mer, and RWP (Random Walk Plot). One can find the relations among organisms, predict the genes in a genome, and research on the function of junk DNA using our workbench.