• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.8
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• pp.27-35
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• 2011

In this paper, performances of the extended QRD-RLS equalizer is analyzed. Since the extended QRD-RLS equalizer is efficiently implemented by systolic array architecture, we analyze performances of this structure with signals of different lengths. By multiplying the frequency responses of the unknown channel and proposed equalizer, we observed the flatness of the overall system function. Through the simulation, it is shown that the performance of the extended QRD-RLS equalizer is remarkably increased with input signals of length 16.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.6
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• pp.1-9
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• 2010

In this paper, we propose a hi-speed/low-power Extended QRD-RLS(QR-Decomposition Recursive Least Squares) equalizer with systolic array structure. In the conventional systolic array structure, vector mode CORDIC on the boundary cell calculates angle of input vector, and the rotation mode CORDIC on the internal cell rotates vector. But, in the proposed structure, it is shown that implementation complexity can be reduced using the rotation direction of vector mode CORDIC and rotation mode CORDIC. Furthermore, calculation time can be reduced by 1/2 since vector mode and rotation mode CORDIC operate at the same time. Through HDL coding and chip implementation, it is shown that implementation area is reduced by 23.8% compared with one of conventional structure.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.25-35
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• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.