• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.2
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• pp.564-574
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• 1996

This paper describes as Electronic Speckle Pattern Interferometry system which has been designed for measuring vibration patterns and quantitative measurement of vibration amplitude fields by using the time average method on a object. Visbility of fringe patterns is more improved by using the phase stepping and frame average method to reduce speckle and electric noise. And a bias vibration is introduced into the reference beam to shift the $\frac{2}{0}$ fringes so that fringe shift algorithms can be used to determine vibration amplitude. The experimental results are compared to those of the FFT analyzer and the FEM model analysis.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.8
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• pp.365-370
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• 2001

We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1196-1198
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• 2005

This paper presents the realization of a four-terminal floating nullor (FTFN), which is simple configuration comprised three OTAs. The external bias currents of the OTAs can electronically adjust the current gain of the proposed FTFN. The realization method is suitable for implementation in monolithic integrated form. To demonstrate the circuit performances, the proposed FTFN was simulated by the use of the PSPICE analog simulation program and implemented using the commercially available OTAs. The simulation and experimental results verifying the performances of the proposed circuit are agreed with the theoretical values. Some application example in the design of the proposed FTFN as electronically tunable active element are also included.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.127-133
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• 1996

In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photoresist reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate form both sides of the main gate. The poly-Si channel layer below the offset oxide is protected form the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of oru new device is the offset region due to the offset oxide. our experimental reuslts show that the offset region, due to the photoresist reflow process, has been sucessfully obtained in order to fabricate the offset gated poly-Si TFTs. The maximum ON/OFF ratio occurs at the L$_{off}$ of 1.1${\mu}$m and exceeds 1X10$^{6}$.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.32-35
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• 2003

Nonlinear parameterization of OLED device from measurements of bias dependence of impedance spectra and parameter extraction using Levenberg-Marquardt complex nonlinear least square regression algorithm based on resistor-capacitor equivalent circuit model enables computer simulation of OLED power driving characteristics in forms of square-wave or sinusoidal output signal at arbitrary conditions. We introduce developed OLED power driving simulation software and discuss transient responses in voltage-or current-controlled operations as well as nonlinear characteristics of OLED, by presenting both the simulation and experimental results. This OLED simulation technique using impedance spectroscopy is extremely useful in predicting performance of the nonlinear device, especially in time-domain analysis of device operation.

• International Journal of Concrete Structures and Materials
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• v.2 no.2
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• pp.153-160
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• 2008

Fracture of prestressed concrete beams is studied with a novel and robust three-dimensional meshfree method. The meshfree method describes the crack as a set of cohesive crack segments and avoids the representation of the crack surface. It is ideally suited for a large number of cracks. The crack is modeled by splitting particles into two particles on opposite sides of the crack segment and the shape functions of neighboring particles are modified in a way the discontinuous displacement field is captured appropriately. A simple, robust and efficient way to determine, on which side adjacent particles of the corresponding crack segment lies, is proposed. We will show that the method does not show any "mesh" orientation bias and captures complicated failure patterns of experimental data well.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.4
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• pp.1-7
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• 1985

In this paper, a more improved threshold voltage model dependent on drain voltage and substrate bias for short - channel enhancement - mode IGFET is presented. Especially, compared with the several recently published models, the error is sufficiently reduced with the precise analysis on the correction factor for short-channel effect and the calculated values using this model are also agreed well with the experimental data about 1$\mu$m - channel length device.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.687-690
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• 2003

Experimental results are presented for gate oxide degradation and its effect on device parameters under negative and positive bias stress conditions using NMOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both hole- and electron-trapping are found to dominate the reliability of gate oxide. However, with changing gate voltage polarity, the degradation becomes dominated by electron trapping. Statistical parameter variations as well as the "OFF" leakage current depend on those charge trapping. Our results therefore show that Si or O bond breakage by electron can be another origin of the investigated gate oxide degradation.gradation.

• Journal of Advanced Marine Engineering and Technology
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• v.29 no.6
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• pp.618-627
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• 2005

In this paper, we have compared and analyzed the performance of high amplifier using Doherty technique to improve linearity and efficiency of base station and repeater Power amplifier for WCDMA. This Doherty amplifier implements with 3dB branch line coupler and $90^{\circ}C$ transmission line The phase offset line is designed to maintain the high linearity and efficiency at the low efficiency Period of the power amplifier CW 1-tone experimental results at the WCDMA frequency $2.11{\sim}2.17GHz$ shows that Doherty amplifier which achieves power add efficiency(PAE) of 50% at 6dB back off the point from maximum output power 52.3 dBm, obtains higher efficiency of 13.3% than class AB Finding optimum bias Point after adjusted gate voltage, Doherty amplifier shows that $IMD_3$ improves 4dB.