• Journal of KIISE:Software and Applications
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• v.30 no.1_2
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• pp.103-116
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• 2003

States explosion due to composition of spaces of data, temporal, and locational values is one of the well-known critical problems which cause difficulty in understanding and analysing real-time systems specified with state-based formal methods. In order to overcome this problem, this paper presents an abstraction method for state minimization based on an abstraction in system specification and an abstraction in system execution. The first is named the syntactic in system specification and an abstraction in system execution. The first is named the syntactic abstraction, through which the patterns of the unconditionally internalized computation and the repetition and selection structures are abstracted. The latter is named the semantic abstraction, through which the patterns of the execution space represented with data. Through the abstractions, the components of a system in specification and execution model is hierarchically organized. The system can be analyzed briefly in the upper level in an skeleton manner with low complexity. The system, however, can be abstraction method for the state minimization and the decrease in analysis complexity through the abstraction with examples.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1150-1156
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• 2008

This paper introduces the PC clustering of the SIMD structure for a distributed processing of on-line contingency to assess a static security of a power system. To execute on-line contingency analysis of a large-scale power system, we need to use high-speed execution device. Therefore, we constructed PC-cluster system using PC clustering method of the SIMD structure and applied to a power system, which relatively shows high quality on the high-speed execution and has a low price. SIMD(single instruction stream, multiple data stream) is a structure that processes are controlled by one signal. The PC cluster system is consisting of 8 PCs. Each PC employs the 2 GHz Pentium 4 CPU and is connected with the others through ethernet switch based fast ethernet. Also, we consider N-1 line contingency that have high potentiality of occurrence realistically. We propose the distributed process algorithm of the SIMD structure for reducing too much execution time on the on-line N-1 line contingency analysis in the large-scale power system. And we have verified a usefulness of the proposed algorithm and the constructed PC cluster system through IEEE 39 and 118 bus system.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.5
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• pp.91-101
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• 2014

In this study, we presented a timing verification method for a passenger car diesel engine management system (EMS) using measurement-based worst-case execution time (WCET) analysis. In order to cope with AUTOSAR-compliant software architecture, a development process model is proposed. In the process model, a runnable is regarded as a test unit and its temporal behavior (i.e. maximum observed execution time, MOET) is obtained along with on-target functionality evaluation results during online unit test. Furthermore, a cost-effective framework for online unit test is proposed. Because the runtime environment layer and the standard calibration environment are utilized to implement test interface, additional resource consumption of the target processor is minimized. Using the proposed development process model and unit test framework, the MOETs of 86 runnables for diesel EMS are obtained with 213 unit test cases. Using the obtained MOETs of runnables, the WCETs of tasks are estimated and the schedulability is evaluated. From the schedulability analysis results, the problems of the initially designed schedule table is recognized and it is fixed by redesigning of the runnable mapping and task offset. Through the various test scenarios, the proposed method is validated.

• Journal of Information Processing Systems
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• v.20 no.1
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• pp.116-130
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• 2024

In the Internet-of-Things (IoT) or blockchain-based network systems, secure keys may be stored in individual devices; thus, individual devices should protect data by performing secure operations on the data transmitted and received over networks. Typically, secure functions, such as a physical unclonable function (PUF) and fully homomorphic encryption (FHE), are useful for generating safe keys and distributing data in a network. However, to provide these functions in embedded devices for IoT or blockchain systems, proper inspection is required for designing and implementing embedded system-on-chip (SoC) modules through overhead and performance analysis. In this paper, a virtual platform (SoC VP) was developed that includes a secure key generation module with a PUF and FHE. The SoC VP platform was implemented using SystemC, which enables the execution and verification of various aspects of the secure key generation module at the electronic system level and analyzes the system-level execution time, memory footprint, and performance, such as randomness and uniqueness. We experimentally verified the secure key generation module, and estimated the execution of the PUF key and FHE encryption based on the unit time of each module.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.133-137
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• 2018

Arduino is a small microcomputer that is used in a variety of industry fields and especially is widely used as an open source hardware IoT device. The multi-tasking method of Arduino is divided into super loop timing and RTOS thread method. The super loop timing method is simple and easy to understand. However, when one task is long, it affects the execution of the next task. In addition, RTOS threading has the advantage of being able to run without being influenced by other work time. However, Arduino, a small microcomputer, has a disadvantage in that, when the number of threads increases, the context switching time of the thread causes additional time not included in the super loop timing method have. In this paper, we use Arduino Uno R3 and FreeRTOS to analyze these different features, and the task for the experiment is to send 8000 digital signals to the built-in LED port. If two tasks of the same size are executed, the super loop method executes 3 ms faster than FreeRTOS multitasking. If multiple tasks are executed simultaneously, superloop type task is sequential execution and difference in execution time between first task and last task is large. FreeRTOS method can be executed concurrently, but execution time delay of about 30 ms occurs in context switching time.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2435-2446
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• 1998

In this paper. We describe a dataflow model for efficient execution of a functional logic language and a method of translation a functional logic language into a dataflow graph. To explore parallelism and intelligent backtracking, we us model in which clause and function are represented as independent dataflow graph. The node denotes basic actions to be performed when the clause and function are executed. The dataflow mechanism allows an operation to be executed as soon as all its operands are available. Since the operations can never be executed earlier, a dataflow model is an excellent base for increasing execution speed. We did decrease a delay time with concurrent execution of dependency analysis and subgoal.

• Journal of Digital Contents Society
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• v.2 no.1
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• pp.9-19
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• 2001

Web robot is an important Internet software technology used in a variety of Internet application software which includes search engines. As Internet continues to grow, implementations of high performance Web robots are urgently demanded. For this, researches specially geared toward performance scalability of Web robots are required. Hoover, because researches are focused mostly on addressing issues related to commercial implementations, scientific researches and studies are not still made on the performance scalability. In this research, Ive choose a Web robot model implemented by fork-join based. multiprocesses. With respect to the model, we evaluate the effect on the collection efficiency that the timeout values set to requests from Web robots to Web servers have. Also, we analysed the behaviors of Web robots by comparing the execution time between the URL extraction and the uniqueness checking for the extracted URLs. as well as by comparing between the computation time and the network time. Based on the analysis result, we suggest the direction for the design of high performance Web robots.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.1008-1012
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• 2009

Obfuscation is known as one of the most effective methods to protect software against malicious reverse engineering transforming the software into more complicated one with still preserving the original semantic. However, obfuscating a program can increase both code size of the program and execution time compared to the original program. In mobile devices, the increases of code size and execution time incur the waste of resources including the increase of power consumption. This paper has analyzed the effectiveness of some high-level obfuscation algorithms as well as their power consumption with implementing them under an embedded board equipped with ARM processor. The analysis results show that there is (are) an efficient obfuscation method(s) in terms of execution time or power consumption according to characteristics of a given program.

• Journal of Computing Science and Engineering
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• v.6 no.1
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• pp.12-25
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• 2012

For real-time systems it is important to obtain the accurate worst-case execution time (WCET). Furthermore, how to improve the WCET of applications that run on multicore processors is both significant and challenging as the WCET can be largely affected by the possible inter-core interferences in shared resources such as the shared L2 cache. In order to solve this problem, we propose an innovative approach that adopts a code positioning method to reduce the inter-core L2 cache interferences between the different real-time threads that adaptively run in a multi-core processor by using different strategies. The worst-case-oriented strategy is designed to decrease the worst-case WCET among these threads to as low as possible. The other two strategies aim at reducing the WCET of each thread to almost equal percentage or amount. Our experiments indicate that the proposed multicore-aware code positioning approaches, not only improve the worst-case performance of the real-time threads but also make good tradeoffs between efficiency and fairness for threads that run on multicore platforms.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.5
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• pp.309-318
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• 1987

In the on-line security analysis of power system, Automatic Contingency Selection (ACS) is commonly used to reduce the number of contingency cases which will be evaluated in detail. This paper describes a fast and reliable ACS method which adopts DC load flow in conjunction with compensation theorem to improve execution time, and applies severity performance index, divided on each limit level for considering overload rate, to make reliable contingency ranking. The method has been tested in IEEE 25 bus system and KEPCO 130 bus actual power system. The results of these tests verify its superiority to both the execution time and reliability, and illustrate its effectiveness for the practical use.