• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.671-677
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• 2001

A RuO$_2$ Schottky photo-detector was designed and fabricated with GaN layers on the sapphire substrate. For good absorption of UV light, an epitaxial structure with undoped GaN(0.5 ${\mu}{\textrm}{m}$)/n￣-GaN(0.1${\mu}{\textrm}{m}$)/n＋-GaN(1.5${\mu}{\textrm}{m}$) was grown by MOCVD. The structure had the carrier concentrations of 3.8$\times$10$^{18}$ cm￣$^3$, the mobility of 283$\textrm{cm}^2$/V.s. After ECR etching process for mesa structure with the diameter of about 500${\mu}{\textrm}{m}$, Al ohmic contact was formed on GaN layer. After proper passivation between the contacts with Si$_3$/N$_4$, was formed on undoped GaN layer. The fabricated Schottky diode had a specific contact resistance of 1.15$\times$10$^{-5}$ ［$\Omega$.$\textrm{cm}^2$］. It has a low leakage current of 305 pA at -5 V, which was attributed by stable characteristics of RuO$_2$ Schottky contact. In optical measurement, it showed the high UV to visible extinction ratio of 10$^{5}$ and very high responsivity of 0.23 A/W at the wavelength of 365nm.

• Korean Journal of Materials Research
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• v.16 no.4
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• pp.225-230
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• 2006

Nanoimprint lithography (NIL) is a novel method of fabricating nanometer scale patterns. It is a simple process with low cost, high throughput and resolution. NIL creates patterns by mechanical deformation of an imprint resist and physical contact process. The imprint resist is typically a monomer or polymer formulation that is cured by heat or UV light during the imprinting process. Stiction between the resist and the stamp is resulted from this physical contact process. Stiction issue is more important in the stamps including narrow pattern size and wide area. Therefore, the antistiction layer coating is very effective to prevent this problem and ensure successful NIL. In this paper, an antistiction layer was deposited and characterized by PECVD (plasma enhanced chemical vapor deposition) method for metal stamps. Deposition rates of an antistiction layer on Si and Ni substrates were in proportion to deposited time and 3.4 nm/min and 2.5 nm/min, respectively. A 50 nm thick antistiction layer showed 90% relative transmittance at 365 nm wavelength. Contact angle result showed good hydrophobicity over 105 degree. $CF_2$ and $CF_3$ peaks were founded in ATR-FTIR analysis. The thicknesses and the contact angle of a 50 nm thick antistiction film were slightly changed during chemical resistance test using acetone and sulfuric acid. To evaluate the deposited antistiction layer, a 50 nm thick film was coated on a stainless steel stamp made by wet etching process. A PMMA substrate was successfully imprinting without pattern degradations by the stainless steel stamp with an antistiction layer. The test result shows that antistiction layer coating is very effective for NIL.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Solar Energy
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• v.17 no.4
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• pp.3-11
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• 1997

Because grain boundaries in polycrystalline silicon act as potential barriers and recombination centers for the photo-generated charge carriers, these defects degrade conversion effiency of solar cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatment, various grid pattern, selective wet etching for grain boundaries, buried contact metallization along grain boundaries, grid on metallic thin film. Pretreatment above $900^{\circ}C$ in $N_2$ atmosphere, gettering by $POCl_3$ and Al treatment for back surface field contributed to obtain a high quality poly-Si. To prevent carrier losses at the grain boundaries, we carried out surface treatment using Schimmel etchant. This etchant delineated grain boundaries of $10{\mu}m$ depth as well as surface texturing effect. A metal AI diffusion into grain boundaries on rear side reduced back surface recombination effects at grain boundaries. A combination of fine grid with finger spacing of 0.4mm and buried electrode along grain boundaries improved short circuit current density of solar cell. A ultra-thin Chromium layer of 20nm with transmittance of 80% reduced series resistance. This paper focused on the grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• The Journal of Korean Academy of Prosthodontics
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• v.57 no.4
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• pp.335-341
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• 2019

Purpose: Chemically strong-acids (HF and $HCl/H_2SO_4$) dual etching implant surfaces have higher strengths of osseointegration than machined implant surfaces. However, the dual acid treatment deteriorates the physical properties of the titanium by weakening the fatigue resistance of the implant and causing microcracks. The removal torque comparison between the dual-acid etched (hydrochloric acid, sulfuric acid, HS) and single-acid etched implants (hydrochloric acid, H) could reveal the efficiency of implant surface acid treatment. Materials and methods: Nine $3.75{\times}4mm$ dual-acid etched SLA implants and nine single-acid etched SLA implants were inserted into New Zealand rabbit tibias. After 10 days, removal torque, roughness, and wetting angle were measured. Results: Mean removal torque values were as follows: Mean removal torque were 9.94 Ncm for HS group and 9.96 Ncm for H group (P=.995). Mean surface roughness value were $0.93{\mu}m$ for HS group and $0.84{\mu}m$ for H group (P=.170). Root mean square roughness (RSq) values were $1.21{\mu}m$ for HS group and $1.08{\mu}m$ for H group (P=.294), and mean wetting angle values were $99^{\circ}$ for HS group and $98^{\circ}$ for H group (P=.829). Statistical analysis showed no significant difference between the removal torques, roughness, or wetting angles of the two groups. Conclusion: In this experiment, we found no significant difference in removal torque, roughness, or wetting angle between dual-acid etched and single-acid etched implants.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.22 no.1
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• pp.5-10
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• 2012

In general, the fabrications of the LEDs with mesa structure are performed grown by MOCVD method. In order to etch and separate each chips, the LEDs are passed the RIE and scribing processes. The RIE process using plasma dry etching occur some problems such as defects, dislocations and the formation of dangling bond in surface result in decline of device characteristic. The SAG method has attracted considerable interest for the growth of high quality GaN epi layer on the sapphire substrate. In this paper, the SAG method was introduced for simplification and fabrication of the high quality epi layer. And we report that the size of selective area do not affect the characteristics of original LED. The diameter of SAG circle patterns were choose as 2500, 1000, 350, and 200 ${\mu}m$. The SAG-LEDs were measured to obtain the device characteristics using by SEM, EL and I-V. The main emission peaks of 2500, 1000, 350, and 200 ${\mu}m$ were 485, 480, 450, and 445 nm respectively. The chips of 350, 200 ${\mu}m$ diameter were observed non-uniform surface and resistance was higher than original LED, however, the chips of 2500, 1000 ${\mu}m$ diameter had uniform surface and current-voltage characteristics were better than small sizes. Therefore, we suggest that the suitable diameter which do not affect the characteristic of original LED is more than 1000 ${\mu}m$.