• 한국표면공학회지
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• 제42권6호
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• pp.267-271
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• 2009

Multicomponent transparent conducting oxide films were deposited on glass substrates at 150 by dual magnetron sputtering of AZO and ITO targets. In the case of mixing a limited amount of ITO (10W), resistivity of TCO films was significantly increased compared to the AZO film; from $3.5{\times}10^{-3}$ to $9.7{\times}10^{-3}{\Omega}{\cdot}cm$. Deterioration of the electrical conductivity is attributed to the decreases in carrier concentration and Hall mobility. Improvement of the conductivity could be obtained for the films prepared with ITO powers larger than 40 W. The lowest resistivity ($\rho$) of $7.3{\times}10^{-4}{\Omega}{\cdot}cm$ was achieved when ITO power was 100 W. Effects of $H_2$ incorporation on the electrical and optical properties of AZO-ITO films were investigated in this work. Addition of small amount of hydrogen resulted in the increase of carrier concentration and the improvement of electrical conductivity. It is apparent that the roughness of AZO-ITO films decreases dramatically after the transition of microstructure from polycrystalline to amorphous phase, which gives practical advantages such as an excellent uniformity of surface and a high etching rate. AZO-ITO films grown at sputtering ambient with hydrogen gas are expected to be applicable to optoelectronic devices such as organic light emitting diodes and flexible displays due to their sufficient electrical and structural properties.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.31-36
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• 2015

전자소자의 다기능, 고밀도, 고성능, 그리고 소형화는 전자 패키지 기술에 초미세 피치 플립 칩, 3D 패키지, 유연 패키지, 등 새로운 기술 패러다임 전환을 가져왔으며, 이로 인해 패키지 된 칩의 열 관리는 소자의 성능을 좌우하는 중요한 요소로 대두되고 있다. Heat sink, heat spreader, TIM, 열전 냉각기, 등 많은 소자 냉각 방법들 중 본 연구에서는 냉매를 이용한 on-chip 액체 냉각 모듈을 Si 웨이퍼에 제작하고, 마이크로 채널 디자인에 따른 냉각 효과를 분석하였다. 마이크로 채널은 딥 반응성 이온 에칭을 이용하여 형성하였고, 3 종류 디자인(straight MC, serpentine MC, zigzag MC)으로 제작하여 마이크로 채널 디자인이 냉각 효율에 미치는 영향을 관찰하였다. 가열온도 $200^{\circ}C$, 냉매 유동속도 150 ml/min의 경우에서 straight MC가 약 $44^{\circ}C$의 높은 냉각 전후의 온도 차를 보였다. 냉매의 흐름과 상 변화는 형광현미경으로 관찰하였으며, 냉각 전후의 온도 차는 적외선현미경을 이용하여 분석하였다.

• The Journal of Advanced Prosthodontics
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• 제8권2호
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• pp.75-84
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• 2016

PURPOSE. To evaluate the effect of various surface treatments on the surface structure and shear bond strength (SBS) of different ceramics. MATERIALS AND METHODS. 288 specimens (lithium-disilicate, leucite-reinforced, and glass infiltrated zirconia) were first divided into two groups according to the resin cement used, and were later divided into four groups according to the given surface treatments: G1 (hydrofluoric acid (HF)+silane), G2 (silane alone-no heat-treatment), G3 (silane alone-then dried with $60^{\circ}C$ heat-treatment), and G4 (silane alonethen dried with $100^{\circ}C$ heat-treatment). Two different adhesive luting systems were applied onto the ceramic discs in all groups. SBS (in MPa) was calculated from the failure load per bonded area (in $N/mm^2$). Subsequently, one specimen from each group was prepared for SEM evaluation of the separated-resin-ceramic interface. RESULTS. SBS values of G1 were significantly higher than those of the other groups in the lithium disilicate ceramic and leucite reinforced ceramic, and the SBS values of G4 and G1 were significantly higher than those of G2 and G3 in glass infiltrated zirconia. The three-way ANOVA revealed that the SBS values were significantly affected by the type of resin cement (P<.001). FIN ceramics had the highest rate of cohesive failure on the ceramic surfaces than other ceramic groups. AFM images showed that the surface treatment groups exhibited similar topographies, except the group treated with HF. CONCLUSION. The heat treatment was not sufficient to achieve high SBS values as compared with HF acid etching. The surface topography of ceramics was affected by surface treatments.

• 한국재료학회지
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• 제24권12호
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• pp.682-688
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• 2014

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.62-62
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• 2003

고밀도 유도결합 플라즈마(high density inductively coupled plasma) 식각은 GaAs 이종접합 양극성 트랜지스터(HBTs)와 고속전자 이동도 트랜지스터(HEMTs)와 같은 GaAs 기반 반도체의 정교한 패턴을 형성하는데 더욱 많이 이용되고 있다 본 연구는 고밀도 플라즈마 소스(source)인 평판형(planar) 고밀도 유도결합 플라즈마 식각장치를 이용하여 $BCl_3$ 와 $BCl_3/Ar$ 가스에 따른 GaAs 식각결과를 비교 분석하였다. 공정변수는 ICP 소스 파워를 0-500W, RIE 척(chuck) 파워를 0-150W, 공정압력을 0-15 mTorr 이었다. 그리고 가스 유량은 20sccm(standard cubic centimeter per minute)으로 고정시킨 상태에서 Ar 첨가 비율에 따른 GaAs의 식각결과를 관찰하였다. 공정 결과는 식각률(etch rate), GaAs 대 PR의 선택도(selectivity), 표면 거칠기(roughness)와 식각후 표면에 남아 있는 잔류 가스등을 분석하였다. 20 $BCl_3$ 플라즈마를 이용한 GaAs 식각률 보다 Ar이 첨가된 (20-x) $BC1_3/x Ar$ 플라즈마의 식각률이 더 우수하다는 것을 알 수 있었다. 식각률 증가는 Ar 가스의 첨가로 인한 GaAs 반도체와 Ar 플라즈마의 충돌로 나타난 결과로 예측된다. $BCl_3$ 와 $BC1_3/Ar$ 플라즈마에 노출된 GaAs 반도체 모두 표면이 평탄하였고 수직 측벽도 또한 우수하였다. 그리고 표면에 잔류하는 성분은 Ga와 As 이외에 $Cl_2$ 계열의 불순물이 거의 발견되지 않아 매우 깨끗함을 확인하였다. 이번 발표에서는 $BCl_3$ 와 $BCl_3/Ar$ 플라즈마를 이용한 GaAs의 건식식각 비교에 대해 상세하게 보고 할 것이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.832-835
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• 2001

We report the structural and electrical properties of hafnium oxide (HfO$_2$) films with tungsten silicide (WSi$_2$) metal gate. In this study, HfO$_2$thin films were fabricated by oxidation of sputtered Hf metal films on Si, and WSi$_2$was deposited directly on HfO$_2$by LPCVD. The hysteresis windows in C-V curves of the WSi$_2$HfO$_2$/Si MOS capacitors were negligible (<20 mV), and had no dependence on frequency from 10 kHz to 1 MHz and bias ramp rate from 10 mV to 1 V. In addition, leakage current was very low in the range of 10$^{-9}$ ~10$^{-10}$ A to ~ 1 V, which was due to the formation of interfacial hafnium silicate layer between HfO$_2$and Si. After PMA (post metallization annealing) of the WSi$_2$/HfO$_2$/Si MOS capacitors at 500 $^{\circ}C$ EOT (equivalent oxide thickness) was reduced from 26 to 22 $\AA$ and the leakage current was reduced by approximately one order as compared to that measured before annealing. These results indicate that the effect of fluorine diffusion is negligible and annealing minimizes the etching damage.

• Journal of Welding and Joining
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• 제24권2호
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Transactions on Electrical and Electronic Materials
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• 제4권2호
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• pp.29-34
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• 2003

Ferroelectric YMnO$_3$ thin films were etched with Ar/C1$_2$ and CF$_4$/C1$_2$ Plasma. The maximum etch rate of YMnO$_3$ thin film was 300 $\AA$/min at a Cl$_2$/Ar gas mixing ratio of 8/2, an RF power of 800 W, a do bias of-200 V, a chamber pressure of 15 mTorr, and a substrate temperature of 3$0^{\circ}C$. From the X-ray photoelectron spectroscopy (XPS) analysis, yttrium was not only etched by chemical reactions with Cl atoms, but also assisted by Ar ion bombardments in Ar/C1$_2$ plasma. In CF$_4$/C1$_2$ plasma, yttrium formed nonvolatile YF$_{x}$ compounds and remained on and the etched surface of YMnO$_3$. Manganese etched effectively by forming volatile MnCl$_{x}$ and MnF$_{y}$. From the X-ray diffraction (XRD) analysis, the (0004) diffraction peak intensity of the YMnO$_3$ thin film etched in Ar/Cl$_2$ plasma shows lower than that in CF$_4$/Cl$_2$ plasma. It indicates that the crystallinty of the YMnO$_3$ thin film is more easily damaged by the Af ion bombardment than the changes of stoichiometry due to nonvolatile etch by-products.cts.s.

• 대한전자공학회논문지
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• 제27권10호
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• pp.106-112
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• 1990

다공질 실리콘을 열산화할 때 산화의 온도 의존성과 IR흡수 스펙트럼을 조사하여 다공질 실리콘외 산화특성을 조사하였다. PSL(porous silicon layer)을 $700^{\circ}C$에서 1시간, $1100^{\circ}C$에서 1시간으로 2단계 습식산화시켜 bulk 실리콘의 열산화막과 같은 성질의 수십 ${\mu}m$두께의 OPSL(oxidized porous silicon layer)을 짧은 시간에 형성시킬 수 있으며, 식각율과 항복전계는 산화온도와 산화 분위기에 크게 의존하는 것으로 나타났다. 이때 PSL의 산화율은 약 390nm/s이고, 항복전계는 1.0MV/cm~2.0MV/cm의 분포를 갖는다. 웨이퍼 휨을 측정하여 고온 열산화시 발생하는 산화막의 stress를 조사하였다. $1000^{\circ}C$ 이상의 고온에서 건식산화할 경우 발생하는 stress는 ${10^2}dyne/{cm^2}~{10^10}dyne/{cm^2}$로 측정되었다.

• 전자공학회논문지D
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• 제36D권5호
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• pp.21-28
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• 1999

Deep Submicron 영역에서 요구되는 고성능 소자로서 자기-정렬된 ESD(Elevated Source/Drain)구조의 MOSFET을 제안하였다. 제안된 ESD 구조는 일반적인 LDD(Lightly-Doped Drain)구조와는 달리 한번의 소오스/드레인 이온주입 과정이 필요하며, 건식 식각 방법을 적용하여 채널의 함몰 깊이를 조정할 수 있는 구조를 갖는다. 또한 제거가 가능한 질화막 측벽을 최종 질화막 측벽의 형성 이전에 선택적인 채널 이온주입을 위한 마스크로 활용하여 hot-carrier 현상을 감소시켰으며, 반전된 질화막 측벽을 사용하여 기존이 ESD 구조에서 문제시될 수 있는 자기-정렬의 문제를 해결하였다. 시뮬레이션 결과, 채널의 함몰 깊이 및 측벽의 넓이를 조정함으로써 충격이온화율(ⅠSUB/ID) 및 DIBL(Drain Induced Barrier Lowering) 현상을 효과적으로 감소시킬 수 있고, 유효채널 길이에 따라 차이가 있으나 두 번의 질화막 측벽을 사용함으로써 hot-carrier 현상이 개선될 수 있음을 확인하였다.