• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.25.2-25.2
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• 2011

Recently, thin film capacitors used for vehicle inverters are small size, high capacitance, fast response, and large capacitance. But its applications were made up of liquid as electrolyte, so its capacitors are limited to low operating temperature range and the polarity. This research proposes using Ni-P alloys by electroless plating as the electrode instead of liquid electrode. Our substrate has a high aspect ratio and complicated shape because of anodic aluminum oxide (AAO). We used AAO because film thickness and effective surface area are depended on for high capacitance. As the metal electrode instead of electrolyte is injected into AAO, the film capacitor has advantages high voltage, wide operating temperature, and excellent frequency property. However, thin film capacitor made by electroless-plated Ni on AAO for full-filling into etched tunnel was limited from optimizing the deposition process so as to prevent open-through pore structures at the electroless plating owing to complicated morphological structure. In this paper, the electroless plating parameters are controlled by temperature in electroless Ni plating for reducing reaction rate. The Electrical properties with I-V and capacitance density were measured. By using nickel electrode, the capacitance density for the etched and Ni electroless plated films was 100 nFcm-2 while that for a film without any etch tunnel was 12.5 nFcm-2. Breakdown voltage and leakage current are improved, as the properties of metal deposition by electroless plating. The synthesized final nanostructures were characterized by scanning electron microscopy (SEM).

• Journal of Welding and Joining
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• 제24권2호
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of Information Display
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• 제10권1호
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• pp.33-36
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• 2009

A new hybrid silicon thin-film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low-temperature poly-Si (LTPS) and a-Si:H TFTs on the same substrate as a backplane of the active-matrix liquid crystal flat-panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the activematrix LCD panel for the gate driver circuit, and a-Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a-Si:H TFT fabrication process in the bottom-gate, back-channel etch-type configuration. The ion-doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of $4\sim5cm^2/V{\cdot}s$ and $0.5cm^2/V{\cdot}s$ for the LTPS and a-Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1" WXGA+(1440$\times$900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a-Si:H TFT gate driver integration circuit

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.658-658
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• 2013

Graphene is an attractive material for various device applications due to great electrical properties and chemical properties. However, lack of band gap is significant hurdle of graphene for future electrical device applications. In the past few years, several methods have been attempted to open and tune a band gap of graphene. For example, researchers try to fabricate graphene nanoribbon (GNR) using various templates or unzip the carbon nanotubes itself. However, these methods generate small driving currents or transconductances because of the large amount of scattering source at edge of GNRs. At 2009, Bai et al. introduced graphene nanomesh (GNM) structures which can open the band gap of large area graphene at room temperature with high current. However, this method is complex and only small area is possible. For practical applications, it needs more simple and large scale process. Herein, we introduce a photosensitive graphene device fabrication using CdSe QD coated nano-porous graphene (NPG). In our experiment, NPG was fabricated by thin film anodic aluminum oxide (AAO) film as an etching mask. First of all, we transfer the AAO on the graphene. And then, we etch the graphene using O2 reactive ion etching (RIE). Finally, we fabricate graphene device thorough photolithography process. We can control the length of NPG neckwidth from AAO pore widening time and RIE etching time. And we can increase size of NPG as large as 2 $cm^2$. Thin CdSe QD layer was deposited by spin coatingprocess. We carried out NPG structure by using field emission scanning electron microscopy (FE-SEM). And device measurements were done by Keithley 4200 SCS with 532 nm laser beam (5 mW) irradiation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.117-117
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• 2008

In MIM capacitor, poly-Si bottom electrode is replaced with metal bottom electrode. Noble metals can be used as bottom electrodes of capacitors because they have high work function and remain conductive in highly oxidizing conditions. In addition, they are chemically very stable. Among novel metals, Ru (ruthenium) has been suggested as an alternative bottom electrode due to its excellent electrical performance, including a low leakage of current and compatibility to high dielectric constant materials. Chemical mechanical planarization (CMP) process has been suggested to planarize and isolate the bottom electrode. Even though there is a great need for development of Ru CMP slurry, few studies have been carried out due to noble properties of Ru against chemicals. In the organic chemistry literature, periodate ion ($IO_4^-$) is a well-known oxidant. It has been reported that sodium periodate ($NaIO_4$) can form $RuO_4$ from hydrated ruthenic oxide ($RuO_2{\cdot}nH_2O$). $NaIO_4$ exist as various species in an aqueous solution as a function of pH. Also, the removal mechanism of Ru depends on solution of pH. In this research, the static etch rate, passivation film thickness and wettability were measured as a function of slurry pH. The electrochemical analysis was investigated as a function of pH. To evaluate the effect of pH on polishing behavior, removal rate was investigated as a function of pH by using patterned and unpatterned wafers.

• Transactions on Electrical and Electronic Materials
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• 제5권6호
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• pp.223-226
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• 2004

The PZT thin films are one of well-known materials that has been widely studied for ferroelectric random access memory (FRAM). We etched the PZT thin films by $CF_{4}/(Cl_{2}+Ar)$ plasma and investigated improvement in etching damage by $O_{2}$ annealing. The maximum etch rate of the PZT thin films was 157 nrn/min and that the selectivity of the PZT thin films to Pt was 3.1 when $CF_{4}(30{\%})$ was added to a $Cl_{2}(80{\%})/Ar(20{\%})$ gas mixing ratio. To improve the ferroelectric properties of PZT thin films after etching, the samples were annealed for 10 min at various temperatures in $O_{2}$ atmosphere. After $O_{2}$ annealing, the remanent polarization of the asdeposited films was $34.6{\mu}/cm^{2}$ and the sample annealed at 650, 550, and $450^{\circ}C$ was 32.8, 22.3, and $18.6{\mu}/cm^{2}$, respectively. PZT thin films with $O_{2}$ annealing at $450^{\circ}C$ retained $77{\%}$ of their original polarization at 106 cycles. Also as the annealing temperature increased, the fatigue properties improved. And the leakage current was decreased gradually and almost recovered to the as-deposited value after the annealing at $450^{\circ}C$.

• 대한전자공학회논문지
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• 제26권4호
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• pp.67-72
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• 1989

부분산화공정(LOCOS : local oxidation of silicon)에서 발생하는 새부리의 길이를 줄이기 위하여 상온 플라즈마 질화막을 잉요한 시로운 공정에 대해 연구하였다. 400W, 100kHz의 교류 전력에 의한 질소 플라즈마로 실리콘 위에 두께가 $100{\AA}$ 미만의 균일한 실리콘 질화막을 형성시킬 수 있었다. 이렇게 형성된 질화막은 실리콘을 4000${\AA}$두께로 산화시키는 공정에서 실리콘의 산화를 효과적으로 방지할 수 있었고 새부리의 길이를 0.2${mu}m$로 감소시킬 수 있다는 것을 SEM 단면도로 확인하였다. 이 길이는 두꺼운 LPCVD 질화막을 이용한 기존의 부분산화공정에서의 0.7${mu}m$ 보다 훨씬 줄어든 것이다. Secco에칭 후 SCM으로 단면을 보았을때 새부리 근처에서 결정 결함을 관찰할 수 없었다. 이 새로운 LOCOS공정으로 $N^+/P^-\;well,\;P^+/N^-$ well 다이오드를 만들어 누설전류를 측정하였다. 그 결과 기존의 LOCOS 공정에 의한 성질보다 우수하거나 동등한 성질을 나타내었다.

• 한국표면공학회지
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• 제49권3호
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• pp.301-306
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• 2016

The effects of nanotexturing and post-etching on the reflection and quantum efficiency properties of diamond wire sawn (DWS) multicrystalline silicon (mc-Si) solar cell have been investigated. The chemical solutions, which are acidic etching solution (HF-$HNO_3$), metal assisted chemical etching (MAC etch) solutions ($AgNO_3$-HF-DI, HF-$H_2O_2$-DI) and post-etching solution (diluted KOH at $80^{\circ}C$), were used for micro- and nano-texturing at the surface of diamond wire sawn (DWS) mc-Si wafer. Experiments were performed with various post-etching time conditions in order to determine the optimized etching condition for solar cell. The reflectance of mc-Si wafer texturing with acidic etching solution showed a very high reflectance value of about 30% (w/o anti-reflection coating), which indicates the insufficient light absorption for solar cell. The formation of nano-texture on the surface of mc-Si contributed to the enhancement of light absorption. Also, post-etching time condition of 240 s was found adequate to the nano-texturing of mc-Si due to its high external quantum efficiency of about 30% at short wavelengths and high short circuit current density ($J_{sc}$) of $35.4mA/cm^2$.

• 한국진공학회지
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• 제13권3호
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• pp.114-119
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• 2004

Si 원료물질로 $SiH_2Cl_2$, N 원료물질로 $NH_3$를 사용하여 증착온도 $550^{\circ}C$에서 P-type Si (100) 기판위에 실리콘 질화막을 원자층 증착 방법으로 형성하고 물리적, 전기적 특성을 평가하였다. 증착된 박막의 두께는 증착 주기의 횟수에 대해 선형적으로 증가하였고, Si와 N 원료물질의 공급량이 $3.0\times10^{9}$ L 일 때 0.13 nm/cycle의 박막 성장속도를 얻을 수 있었다. 원자층 증착된 박막의 물리적 특성을 기존의 저압화학증착 방법에 의해 증착된 박막과 비교한 결과, 원자층 증착 방법을 사용함으로써 기존의 방법보다 증착온도를 $200 ^{\circ}C$이상 낮추면서도 굴절률 및 습식에칭 속도 측면에서 유사한 물성을 가진 실리콘 질화막을 형성할 수 있었다. 특히, 원자층 증착된 박막의 누설 전류밀도는 3 MV/cm의 전기장에서 0.79 nA/$\textrm{cm}^2$로서 저압화학증착 방법에 의해 증착된 질화막의 6.95 nA/$\textrm{cm}^2$보다 우수하였다.

• Restorative Dentistry and Endodontics
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• 제36권4호
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• pp.280-289
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• 2011

연구목적: 본 연구의 목적은 다양한 소수성을 지닌 최신 상아질 접착시스템과 저수축 silorane 레진의 미세인장결합강도를 평가하는 것이다. 연구 재료 및 방법: 36개의 갓 발치된 제3대구치를 이용했다. Low-speed diamond saw를 사용하여 교합면에 평행하게 치관을 잘라 middle dentin을 노출시켰다. 치아를 무작위로 9 group으로 나눴다. Silorane self-etch adhesives (SS), SS + phosphoric acid etching (SS + pa), Adper Easy bond (AE), AE + Silorane system bonding (AE + SSb), Clearfil SE bond (CSE), CSE + SSb, All-Bond 2 (AB2), AB2 + SSb, All-Bond 3 (AB3). 접착제를 적용한 후에 Filtek LS (3M ESPE)를 2 mm씩 3회 적층충전하였다. 각 층은 40s씩 광중합하였다. 0.8 mm ${\times}$ 0.8 mm stick을 Micro Tensile Tester로 1 mm/min cross-head speed의 인장력을 가하였다. 파절양상를 관찰하기 위해 광학현미경을 이용하였다. 5가지 접착제의 소수성정도를 결정하기위해 water sorption test하였다. 결과: silorane 레진과 5가지 접착제의 ${\mu}TBS$: SS, 23.2 ${\pm}$ 6.9 MPa; CSE, 19.4 ${\pm}$ 4.4 MPa; AB3, 30.3 ${\pm}$ 4.0 MPa; AB2와 AE, no bond. Additional layering of SSb: CSE + SSb, 26.2 ${\pm}$ 10.3 MPa; AB2 + SSb, 33.9 ${\pm}$ 7.3 MPa; AE + SSb, no bond. 높은 ${\mu}TBS$는 cohesive failure와 관련있었다. SS는 낮은 가장 낮은 water sorption을 보였고 다음으로 AB3, AE, CSE, AB2 순서였다. AE는 가장 높은 용해도를 나타냈고 다음으로 CSE, AB2였다. 결론: 접착제의 소수성이 증가할수록, silorane 레진의 접착강도도 증가하였다. 비전용접착제 위에 silorane adhesive bonding을 layering하는 것은 AB2 + SSb 그룹에서만 결합강도를 유의하게 증가시켰다. AB3는 SS와 유사한 ${\mu}TBS$ & water sorption을 나타냈다. 따라서 AB3는 siloran resin을 접착시키는데 SS를 대체할만한 경쟁력있는 접착제이다.