• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.830-833
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• 2003

This paper describes the fabrication and characteristics of 3C-SiCOI sotctures by SDB and etch-back technology for high-temperature MEMS applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si(001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The wafer bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR. The strength of the bond was measured by tensile strengthmeter. The bonded interface was also analyzed by SEM. The properties of fabricated 3C-SiCOI structures using etch-back technology in TMAH solution were analyzed by XRD and SEM. These results indicate that the 3C-SiCOI structure will offers significant advantages in the high-temperature MEMS applications.

• Applied Science and Convergence Technology
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• v.23 no.4
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• pp.169-178
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• 2014

Fluid model based numerical analysis is done to simulate a low damage etch back system for 20 nm scale semiconductor fabrication. Etch back should be done conformally with very high material selectivity. One possible mechanism is three steps: reactive radical generation, adsorption and thermal desorption. In this study, plasma generation and transport steps are analyzed by a commercial plasma modeling software package, CFD-ACE+. Ar + $CF_4$ ICP was used as a model and the effect of reactive gas inlet position was investigated in 2D and 3D. At 200~300 mTorr of gas pressure, separated gas inlet scheme is analyzed to work well and generated higher density of F and $F_2$ radicals in the lower chamber region while suppressing ions reach to the wafer by a double layer conducting barrier.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.4
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• pp.327-331
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• 2008

An in-line wet etch/cleaning system was established for the research and development in wet etch process as a formation of electrode such as metal or transparent conductive oxide layer. A reverse moving system was equipped in the in-line wet etch/cleaning system for the alternating motion of glass substrate in a wet etch bath of the system. Therefore, it was possible for the glass substrate to be moved back and forth and it was possible to reduce the size of the system by using the reversing moving system. For the effect of the alternating motion of substrate on the etch rate in the in-line wet etch bath, indium tin oxide(ITO) patterns were obtained through wet etch process in the in-line system in which the substrate was moved back and forth. From the CD(critical dimension) skews resulted from the ADI CD and ACI CD of the ITO patterns, it was concluded that the alternating motion of glass substrate are possible to be applied to the mass production of wet etch process.

• New & Renewable Energy
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• v.4 no.2
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• pp.74-80
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.390-393
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.715-718
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• 2008

An in-line wet etch/cleaning system was established for the research and development in wet etch process. The system was equipped with a reverse moving system for the reduction in the size of the in-line wet etch/cleaning system and it was possible for the glass substrate to be moved back and forth and alternated in a wet etch bath. For the comparison of the effect of the normal motion and that of the alternating motion on the in-line wet etch process, indium tin oxide(ITO) pattern was obtained through both wet etch process conditions. The results showed that the alternating motion is not inferior to the normal motion in etch rate and in etch uniformity. It is concluded that the alternating motion is possible to be applied to the in-line etch process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.711-714
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• 2004

A new design for improving the aperture ratio of bottom emission type AMOLED is investigated. In conventional, the TFT of AMOLED fabrication method is "Etch Stopper (7-mask)", so the aperture ratio is limited in 28${\sim}$33% by Cs(Storage Capacitor). A high aperture ratio TFT is designed by using BCE(Back Channel Etching 5-mask) fabrication way and the aperture ratio is up to 40% shown in 2.2"AMOLED display.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.57-63
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• 2008

In this paper, the dependence of MOSFET performance on the channel stress is characterized in depth. The tensile and compressive stresses are applied to CMOSFET using a nitride film which is used for the contact etch stop layer (CESL). Drain current of NMOS and PMOS is increased by inducing tensile and compressive stress, respectively, due to the increased mobility as well known. In case of NMOS with tensile stress, both decrease of the back scattering ratio ($\tau_{sat}$) and increase of the thermal injection velocity ($V_{inj}$) contribute the increase of mobility. It is also shown that the decrease of the $\tau_{sat}$ is due to the decrease of the mean free path ($\lambda_O$). On the other hand, the mobility improvement of PMOS with compressive stress is analyzed to be only due to the so increased $V_{inj}$ because the back scattering ratio is increased by the compressive stress. Therefore it was confirmed that the device performance has a strong dependency on the channel back scattering of the inversion layer and thermal injection velocity at the source side and NMOS and PMOS have different dependency on them.

• Journal of Information Display
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• v.13 no.2
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.