• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.97-98
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• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

• 한국인쇄학회지
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• 제12권1호
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• pp.67-80
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• 1994

Electrochrominm is a phenomenon of reversible change in optical properties produced electrochromically. Among the several organic type electrochromic displays(ECD), the one based on viologen solution is still attractive and become of the possibility for choosing various colors by introducing different substituents in viologen molecules. But these has been rather a severe problem in this type of ECD, which is the erasing failure caused by the recrystallized molecule sticking to the display electrode.This paper was investigated on developing a new class of composite materials which consists of the mixture of BV2+ . 2BF4-, TMPD with TBABF4 as supporting electrolyte to overcome the above mentioned problem of viologen solution.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.911-913
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• 2008

In this work, nonvolatile memory (NVM) devices for system on panel of flat panel display (FPD) were fabricated using low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology with an oxide-nitride-oxynitride (ONOn) stack structure on glass. The results demonstrate that the NVM devices fabricated using the ONOn stack structure on glass have suitable switching characteristics for data storage with a low operating voltage, a threshold voltage window of more than 1.8 V between the programming and erasing (P/E) states after 10 years and its initial threshold voltage window (${\Delta}V_{TH}$) after $10^5$ P/E cycles.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.113-116
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• 2003

The sustain discharge mode using various auxiliary pulses was proposed to improve both the luminance and luminous efficiency of ac-plasma display panel (ac-PDP). It was found that the various auxiliary pulses, which were applied at the rising and falling time of the sustain pulse, played a role in strengthening both the main and self-erasing discharges. As a result, the sustain waveforms with auxiliary pulse improved both the luminance of 23 % and the luminous efficiency of 36 %, when compared with the conventional sustain waveform without auxiliary pulse.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.358-358
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• 2010

To improve the programming/erasing speed and leakage current of multiple dielectric stack tunnel barrier engineering (TBE) Non-volatile memory, We propose a new concept called staggered structure of TBE memory. In this study, We fabricated staggered structure capacitor on $Si_3N_4$ stacked HfAlO and measured C-V curve that can observe tunneling characteristic of this device as various annealing temperature compared with that of single layer $SiO_2$ capacitor.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.32-39
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• 2008

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

• 한국전자통신학회논문지
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• 제6권1호
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• pp.118-122
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• 2011

플래시메모리의 쓰기나 소거 등의 프로그래밍 동작을 위해서는 각기 다른 고전압이 필요하며, 이를 위해서 차지펌프회로가 사용되어 왔다. 본 논문에서 제안되는 차지펌프회로는 VCO를 이용하여 외부에서 인가되는 기준전압과 차지펌프의 출력이 일치하도록 클락 주파수를 조절해줌으로서 공정에 의한 오차뿐만 아니라 차지펌프의 각 단을 구성하는 MOSFET의 바디효과에 관계없이 예측 가능한 출력을 발생하는 회로이다.

• 한국콘크리트학회:학술대회논문집
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• 한국콘크리트학회 2000년도 봄 학술발표회 논문집
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• pp.357-362
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• 2000

This Paper presents dynamic analysis of underground R/C Subway Structure, subjected to seismic actions. Earthquakes brought serious damage to RC subway Structure. Foe studying the collapse mechanism of underground RC Subway, seismic of a subway station is simulated in using FEM program ASP2000 of two-dimension based on the path dependent RC elastic model, soil foundation and interfacial models. The shear failure of intermediate vertical columns is founds to be the major cause of the structural collapse. According to FEM simulation of the failure mechanism, it is considered that the RC column would lose axial load carrying capacity after the occurrence of the localized diagonal shear cracks , and sudden failure of the outer frame would be followed. Specially, the shear stress in the middle slab reaches maximum shear capacity. So, the Structure would fail in the middle slab as a result of erasing the vertical ground motion computation.

• 전자공학회논문지A
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• 제30A권5호
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• pp.1-15
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• 1993

In DQDB networks, the bandwidth can be increased considerably be using the EN(Erasure Node) algorithms and DR(Destination Release) algorithms. However, the important issue in implementing them is using method of extra capacity fairly. To improve it, this paper proposes AEN(Adaptive Erasure Node) algorithm which erasure function is activated by network traffic load. Its functional architecture consists of SESM, RCSM, LMSM in addition to the basic DQDB state machines (DQSM, RQM). The SESM and RCSM state machines are placed in front of the DQSM and RQM state machines in order for the node to take advantage of the newly cleared slots. This paper also presents some simulation results showing the effect of AEN algorithm on access delay, throughput and segment erasing ratio in the single and multiple priority networks. The results show that the AEN algorithm offer the better performance characteristics than existing algorithms under overload conditions.