• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.643-646
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• 2005

We present new ramp-reset waveforms that realize fast addressing in AC-PDPs. These waveforms distort the distribution of wall charges on the surface of a phosphor layer: hence, the enhanced electric field helps to ignite a cell faster. They also reduce the black luminance: the divide of erasing ramp down discharges into two parts, i.e. a surface discharge and a vertical discharge, makes lower luminance.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.217-219
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• 2001

플래쉬 메모리는 데이터 저장 및 변경이 가능한 비휘발성 메모리로 가벼운 무게, 낮은 전력 소모, 충격에 대한 저항성과 빠른 데이터 처리 능력 때문에 이동형 컴퓨터 시스템에서 사용하기에 적당하다. 그러나 플래쉬 메모리는 덮어쓰기(update-in-place)가 불가능하고 각 메모리 셀에 대해 초기화 작업(erasing operation)의 수가 제한되어 있다. 이러한 단점들을 고려하여 세그먼트의 데이터 중 유효 데이터의 비율과 hot 데이터(가까운 시간 안에 update가 될 것이라는 예상되는 data)의 수, 세그멘트가 초기화되었던(easing) 횟수 등을 고려한 새로운 초기화 기법(cleaning policy)을 제안하고자 한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• The KIPS Transactions:PartB
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• v.9B no.4
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• pp.509-516
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• 2002

This paper proposes an efficient algorithm which recognizes the mixed document image consisting of the images, texts, tables, and straight lines. This system is composed of three steps. The first step is the detection of rotation angle for complementing skewed images, the second is detection of erasing an unnecessary background region and last is the classification of each component included in document images. This algorithm performs preprocessing of detecting rotation angles and correcting documents based on the detected rotation angles in order to minimize the error rate by skewness of the documentation. We detected the rotation angie using only horizontal and vertical components in document images and minimized calculation time by erasing unnecessary background region in the detecting process of component of document. In the next step, we classify various components such as image, text, table and line area included in document images. we applied this method to various document images in order to evaluate the performance of document recognition system and show the successful experimental results.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.254.2-254.2
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• 2014

The Transmission Fourier Transform Infrared spectroscopy (FTIR) of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000~2300 cm-1. It indicated that the existence of many silicon phases and defect sources in the matrix of the SiOx films. The total hysteresis width is the sum of the flat band voltage shift (${\Delta}VFB$) due to electron and hole charging. At the range voltage sweep of ${\pm}15V$, the ${\Delta}VFB$ values increase of 0.57 V, 1.71 V, and 13.56 V with 1/2, 2/1, and 6/1 samples, respectively. When we increase the gas ratio of SiH4/N2O, a lot of defects appeared in charge storage layer, more electrons and holes are charged and the memory window also increases. The best retention are obtained at sample with the ratio SiH4/N2O=6/1 with 82.31% (3.49V) after 103s and 70.75% after 10 years. The high charge storage in 6/1 device could arise from the large amount of silicon phases and defect sources in the storage material with SiOx material. Therefore, in the programming/erasing (P/E) process, the Si-rich SiOx charge-trapping layer with SiH4/N2O gas flow ratio=6/1 easily grasps electrons and holds them, and hence, increases the P/E speed and the memory window. This is very useful for a trapping layer, especially in the low-voltage operation of non-volatile memory devices.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.1
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• pp.83-89
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• 2013

In order to reduce the power consumption in international standard IEC62087, the luminance efficiency should be improved at the low discharge load rather than at the high discharge load. Thus, this paper analysed the characteristics of the discharge at the panels with ITO Gap of $65{\mu}m$, $80{\mu}m$, and $100{\mu}m$ in 50-inch PDP with FHD resolution. It was well known that the long gap panel improves the luminance and the luminous efficiency. However, it is very difficult to drive the panel due to high driving voltage. When the normal driving method was applied at the panel with ITO gap of $100{\mu}m$, the phenomenon of the double peak was generated in the sustain period. We confirmed that main factor of the double peak is the self-erasing discharge. When the CLHS driving method was applied at the panel with ITO gap of $100{\mu}m$, the self-erasing discharge was improved in the sustain period. Also, the $V_S$ and $V_A$ minimum voltage of the CLHS driving method decreased about 9V and 12V compared with those of the normal driving method. Moreover, when the CLHS driving method was applied to the panel with ITO gap of $100{\mu}m$, the luminance and the luminous efficiency increased compared with those of the normal driving method. The luminance and the luminous efficiency greatly increased at the low discharge load. The less discharge load, the higher increase rate of the luminance and the luminous efficiency. Especially, the luminous efficiency at ITO gap of $100{\mu}m$ increased about 26.3% at the discharge load of 4% compared with that at ITO gap of $65{\mu}m$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.4
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• pp.314-320
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• 1998

In this study, we have investigated crystallization properties of $Te_x(Sb_{85}Ge_{15})_{100-x}$ (x=0.3, 0.5, 1.0) thin films prepared by thermal evaporation. The change of reflectance according to phase change from amorphous to crystalline phases with annealing and exposure of diode laser is measured b the n&k analyzer and the surface morphology between amorphous and crystalline phase is analyzed by SEM and AFM. The difference in reflectance($\DeltaR$) between amorphous and crystalline phase appears approximately 20% at the diode laser wavelength, 780nm in all prepared films. Especially, the reflectance difference,$\DeltaR$ comes up to about 30% in $Te_{0.5}(Sb_{85}Ge_{15})_{99.5}$ thin film. Also, amorphous-to-crystalline phase change is observed in all prepared films. As a result of the measurement of the reflectance using diode laser, the reflectance is increased in proportion to the laser power and exposure time in all films. As a result of observing each film with the SEM and AFM, the surface morphology of the annealed and the exposed films are evidently increased than those of as-deposited films. The fast crystallization is occurred by increasing in Te content. Therefore, we conclude that the $Te_{0.5}(Sb_{85}Ge_{15})_{99.5}$ and $Te_1(Sb_{85}Ge_{15})_{99}$ thin films can be evaluated as an attractive optical recording medium with high contast ratio and fast erasing time due to crystallization.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.407-410
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• 2005

For reducing DFC(Dynamic False Contour), we propose a new PDP driving method by rearrangement of sub-fields. The proposed method constructs a frame using 16 sub-fields for expressing 256 gray levels. Although the number of sub-fields increases, the display time increases compared to the conventional 8 sub-fields driving method. This increase in display time is achieved by properly using both selective writing and selective erasing for each sub-field.