• 한국의학물리학회지:의학물리
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• 제2권2호
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• pp.175-182
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• 1991

본 논문은 인공폐의 설계및 임상진단을 위한 허파기능의 연구 및 호흡생리의 요체인 폐모세 혈관내 혈액의 Hb와 가스상 산소의 비선형 결합특성을 규명할 수 있는 새로운 산소포화 모델을 전기적 등가회로에 기초하여 유도하였다. 새로이 유도된 산소포화 모텔은 종래의 모델에 비해 훨씬 간단하고, 광범위한 pH 및 각 생리 parameter 등의 변동에도 정확히 적용될 수 있었을 뿐 아니라, 결합반응과 등가인 2단 및 4단 RC 전기적 등가회로의 Simulation 결과로 부터, Hb 와 산소의 비선형 결합특성은 2단계의 복합 반응으로 취급하는 것이 타당함을 확인하였다.

• Journal of Advanced Marine Engineering and Technology
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• 제22권5호
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• pp.617-625
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• 1998

A passive energy recovery snubber for high-power-factor boost rectifier, in which the main switch is implemented with a MOSFET, is described in terms of the equivalent circuits that are operational during turn-on and turn-off sequences. These equivalent circuits are analyzed so that the overshoot voltage across the main switch, the snubber current, and the turn-off transition time can be predicted analytically. From these results, the normalized overshoot voltage is reduced to 1 as $_W2T_on$ varies from zero to $\pi$/2, and then it is fIxed at 1 for $_W2T_on$> $\pi$/2. The peak snubber inductor current is directly proportional to the input current. The turn-offtransition time wltoffvaries from 0 to 2.57, depending on $_W2T_on$. The main switch combined with proposed snubber can be turned on with zero current and turned off at limited voltage stress. The high-power-factor boost rectifier with proposed snubber is implemented, and the experimental results are presented to confirm the validity of proposed snubber.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.668-676
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• 1998

A passive energy recovery snubber for high-power-factor boost rectifier, in which the main switch is described in terms of the equivalent circuits that are operational during turn-on and turn-off sequences. These equivalent circuits are analyzed so that the overshoot voltage across the main switch, the snubber current, and the turn-off transition time can be predicted analytically. The main switch combined with proposed snubber can be turned on with zero current and turned off at limited voltage stress. The high-power-factor boost rectifier with proposed snubber is implemented, and the experimental results are presented to confirm the validity of proposed snubber.

• 전기학회논문지
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• 제56권11호
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• pp.1967-1971
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• 2007

In this paper, we verified basic forms and equivalent circuits of spiral inductors and various kinds of parasitics of equivalent circuits by using HFSS and Nexxim program that were 3-D EM analysis tools, and fabrication on-chip spiral inductors using Hynix's 0.25um 1-poly and 5-metal CMOS process. Comparing with PGS(patterned ground shield) and NPGS(non patterned ground shield) of spiral inductors of 3.5 turn, 4.5 turn and 5.5 turn, etc, the application of PGS could improve maximum Q value by 8-12%.

• Journal of Power Electronics
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• 제2권2호
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• pp.139-145
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• 2002

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitice between the drain/collertor of an active switch and frame ground through its heat sink may generate the commom-mode conducted noise. We have proposed a balanced switching converter circuit, whitch is an effective way to reduce the commom-mode converter version of the balanced switching converter was presented and the mechanism of the commom-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switch converter circuit and presents a buck-boost converter version of the blanced switching converter. The feature of common-mode niose reduction is confirmed by experimental resuits and the mechanisem of the commom-mode niose reduction is explained using equivalent circuits.

• 대한전자공학회논문지
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• 제10권6호
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• pp.11-24
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• 1973

본 논문에서는 전압안정 및 전류안정부저항영역을 갖는 2단자회로를 해석함에 있어서 따로 입력변화의 함수로서 표시되는 등가주전력을 사용하였고 부저항회로에 대한 간단한 새로운 통일된 해석을 할 수 있음을 도시법을 기초로 하여 제시하였다. 이 해석에 의거한 설계방법의 예로서 접합트랜지스터를 사용한 부성저항회로구성을 하였으며 이 회로를 기본으로 하여 SCR, GTO-SCR 및 SSS 특성의 한 모데링회로를 제안하였다. 이들 모데링회로의 촙핑회로, 톱니파발생회로 및 교류위상제어회로로서의 응용예와 그 특성을 아울러 검토하였다.

• 산업기술연구
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• 제13권
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• pp.59-69
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• 1993

Using two current conveyors with the grounded capacitors and resistors, this paper proposed equivalent circuits which can realize the floating L and the floating FDNR. To find out their characteristics, we experiment with these circuits instead of the floating L of the low-pass filter and the floating FDNR of the high-pass filter respectively. Comparing theoretical values with experimental ones, values of the proposed floating L represent the error of 5 percents in the frequency range from 5 KHz to 25 KHz, and values of the floating FDNR represent the error of 5 percents in the range from 8 KHz to 25 KHz. So the proposed floating L and the FDNR circuits are expected to be implemented with current conveyors of an IC.

• 천문학논총
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• 제13권1호
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• pp.123-128
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• 1998

The Blandford-Znajek process, which extracts the rotational energy of the supermassive black hole at the center of an active galactic nucleus, is now well explained and educated through the electronic circuit analysis established by Macdonald and Thorne. The Macdonald-Thorne circuits consist of the batteries and resistances of the central black hole and the astrophysical region around the accretion disk. In this letter we will consider the possibility whether we can connect coils and condensers in such circuits or not. If possible, that may explain a sudden corona-phenomenon in an active galactic nucleus. We conclude that a flash of order $\~5\times10^{40}\;ergs\;s^{-1}$ can occur around a $\~10^9M_\bigodot$ black hole through this process.

• 전자공학회논문지C
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• 제34C권3호
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• pp.11-22
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• 1997

This paper presents the design and implementation of an efficient algorithm for detecting untestable paths in multi-level circuits. Transforming multi-level circuit into a multiplexor-based one through BDD(binary decision diagram)construction, the proposed algorithm detects untestable paths in the transformed circuits. By constructing ENF (equivalent normal form) only for reconvergent paths, the proposed system detects and removes untestable paths efficiently in terms of the run-time and memory usage. Experimental results for MCNC/ISCAS benchmark circuits show that the system efficiently detects and removes untestable paths. The run-time and memory usage have been reduced by 37.7% and 60/9%, respectively, comapred to the previous methods.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2011년도 전기공동학술대회 논문집
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• pp.194-194
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• 2011