• Title/Summary/Keyword: Epi layer

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The development of the photoreflectance program for the analysis of semiconductor optical properties

  • Shin, Sang-Hoon;Kim, Geun-Hyeong
    • Journal of the Korea Society of Computer and Information
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    • v.27 no.8
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    • pp.211-218
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    • 2022
  • In this paper, a computer simulation program was developed to interpret the results measured by photoreflectance spectroscopy. The developed program is implemented so that the user can easily change the factors required for optical modulation characteristic interpretation, and the result of the value can be checked simultaneously with the actual measurement result. The results obtained by photoreflectance spectroscopy are obtained by mixing a third derivative function form (TDFF) modulated around a bandgap with a Franz-Keldysh oscillation (FKO) signal due to an electric field at a surface and an interface higher than the bandgap. Through the computer simulation program, the optical characteristics that appear in the GaSb Epi layer formed as a single layer were analyzed, and very useful results were obtained by specializing in optical modulation analysis. In addition, a Fast Fourier Transform (FFT) analysis tool was added to facilitate frequency characteristics analysis of FKO.

The effect of deep level defects in SiC on the electrical characteristics of Schottky barrier diode structures (깊은 준위 결함에 의한 SiC SBD 전기적 특성에 대한 영향 분석)

  • Lee, Geon-Hee;Byun, Dong-Wook;Shin, Myeong-Cheol;Koo, Sang-Mo
    • Journal of IKEEE
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    • v.26 no.1
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    • pp.50-55
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    • 2022
  • SiC is a power semiconductor with a wide bandgap, high insulation failure strength, and thermal conductivity, but many deep-level defects. Defects that appear in SiC can be divided into two categories, defects that appear in physical properties and interface traps that appear at interfaces. In this paper, Z1/2 trap concentration 0 ~ 9×1014 cm-3 reported at room temperature (300 K) is applied to SiC substrates and epi layer to investigate turn-on characteristics. As the trap concentration increased, the current density, Shockley-read-Hall (SRH), and Auger recombination decreased, and Ron increased by about 550% from 0.004 to 0.022 mohm.

Design of ISL(Intergrated Schottky Logic) for improvement speed using merged transistor (속도 향상을 위한 병합트랜지스터를 이용한 ISL의 설계)

  • 장창덕;백도현;이정석;이용재
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.21-25
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    • 1999
  • In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. In the result, we get amplitude of logic voltage of 200mV, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26ns in AC characteristic output of Ring-Oscillator connected Gate.

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Optimization simulation for High Voltage 4H-SiC DiMOSFET fabrication (고전압 4H-SiC DiMOSFET 제작을 위한 최적화 simulation)

  • Kim, Sang-Cheol;Bahng, Wook;Kim, Nam-Kyun;Kim, Eun-Dong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.353-356
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    • 2004
  • This paper discribes the analysis of the I-V characteristics of 4H-SiC DiMOSFET with single epi-layer Silicon Carbide has been around for over a century. However, only in the past two to three decades has its semiconducting properties been sufficently studied and applied, especially for high-power and high frequency devices. We present a numerical simulation-based optimization of DiMOSFET using the general-purpose device simulator MINIMIS-NT. For simulation, a loin thick drift layer with doping concentration of $5{\times}10^{15}/cm^3$ was chosen for 1000V blocking voltage design. The simulation results were used to calculate Baliga's figure of Merit (BFOM) as the criterion structure optimization and comparison.

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The AC Breakdown Properties of Gate Oxide Layer in MOSFET (MOSFET에서 Gate Oxide층의 교류 절연파괴 특성)

  • Park, Jung-Goo;Song, Jung-Woo;Ko, Si-Hyoen;Cho, Kyung-Soon;Shin, Jong-Yeol;Lee, Yong-Woo;Hong, Jin-Woong
    • Proceedings of the KIEE Conference
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    • 1999.11d
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    • pp.941-943
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    • 1999
  • In this paper, the AC breakdown properties to investigate the electrical properties of gate oxide layer in MOSFET was studied. 5 inch arsenic epi-wafer is selected as an experimental specimen, the power MOSFET of a general MOS structure was made. In order to analyze the physical properties of the specimen, the SIMS(secondary ion mass spectroscopy) was used. As the experimental condition, the experiment al of the AC breakdown characteristics was performed when the thickness of gate oxide layer is $600[\AA]$ and $800[\AA]$, the resistivity is $1.2[\Omega{\cdot}cm]$, $1.5[\Omega{\cdot}cm]$ and $1.8[\Omega{\cdot}cm]$, and the diffusion time is 110[min] and 150[min] in temperature $30[^{\circ}C]{\sim}100[^{\circ}C]$. From the analysis result of the SIMS spectrum, it is confirmed that the dielectric strength is decreased by contribution of the impurities ad dition as increasing in thickness of the gate oxide layer in MOSFET.

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Design of a high speed and high intergrated ISL(Intergrated Schottky Logic) using a merged transistor (병합트랜지스터를 이용한 고속, 고집적 ISL의 설계)

  • 장창덕;이용재
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.05a
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    • pp.415-419
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    • 1999
  • Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

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The characteristics of electrochemical etch-stop in THAH/IPA/pyrazine solution (TMAH/IPA/pyrazine 용액에서의 전기화학적 식각정지특성)

  • Chung, G.S.;Park, C.S.
    • Journal of Sensor Science and Technology
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    • v.7 no.6
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    • pp.426-431
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    • 1998
  • This paper describes electrochemical etch-stop characteristics in THAH/IPA/pyrazine solution. I-V curves of n- and p-type Si in THAH/IPA/pyrazine solution were obtained. OCP(Open Circuit Potential) and PP (Passivation Potential) of p-type Si were -1.2 V and 0.1 V, and of n-type Si were -1.3 V and -0.2 V, respectively. Both n- and p-type Si, etching rates were abruptly decreased at potentials anodic to the PP. The etch-stop characteristics in THAH/IPA/pyrazine solution were observed. Since accurate etching stop occurs at pn junction, Si diaphragms having thickness of epi-layer were fabricated. Etching rate is highest at optimum etching condition, TMAH 25wt.%/IPA 17vol.%/pyrazine 0.1g/100ml. thus the elapsed time of etch-stop was reduced.

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Analysis on the Scaling of MOSFET using TCAD (TCAD를 이용한 MOSFET의 Scaling에 대한 특성 분석)

  • 장광균;심성택;정정수;정학기;이종인
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.05a
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    • pp.442-446
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    • 2000
  • The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased parking density. Therefore, it was interested in scaling theory, and full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot carriers in different MOSFET structures. MOSFET structures investigated in this study include a conventional MOSFET with a single source/drain, implant a lightly-doped drain(LDD) MOSFET, and a MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and those are analyzed using TCAD(Technology Computer Aided Design) for scaling and simulation. The scaling has used a constant-voltage scaling method, and we have presented MOSFET´s characteristics such as I-V characteristic, impact ionization, electric field and recognized usefulness of TCAD, providing a physical basis for understanding how they relate to scaling.

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Enhancing Gamma-Neutron Shielding Effectiveness of Polyvinylidene Fluoride for Potent Applications in Nuclear Industries: A Study on the Impact of Tungsten Carbide, Trioxide, and Disulfide Using EpiXS, Phy-X/PSD, and MCNP5 Code

  • Ayman Abu Ghazal;Rawand Alakash;Zainab Aljumaili;Ahmed El-Sayed;Hamza Abdel-Rahman
    • Journal of Radiation Protection and Research
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    • v.48 no.4
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    • pp.184-196
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    • 2023
  • Background: Radiation protection is crucial in various fields due to the harmful effects of radiation. Shielding is used to reduce radiation exposure, but gamma radiation poses challenges due to its high energy and penetration capabilities. Materials and Methods: This work investigates the radiation shielding properties of polyvinylidene fluoride (PVDF) samples containing different weight fraction of tungsten carbide (WC), tungsten trioxide (WO3), and tungsten disulfide (WS2). Parameters such as the mass attenuation coefficient (MAC), half-value layer (HVL), mean free path (MFP), effective atomic number (Zeff), and macroscopic effective removal cross-section for fast neutrons (ΣR) were calculated using the Phy-X/PSD software. EpiXS simulations were conducted for MAC validation. Results and Discussion: Increasing the weight fraction of the additives resulted in higher MAC values, indicating improved radiation shielding. PVDF-xWC showed the highest percentage increase in MAC values. MFP results indicated that PVDF-0.20WC has the lowest values, suggesting superior shielding properties compared to PVDF-0.20WO3 and PVDF-0.20WS2. PVDF-0.20WC also exhibited the highest Zeff values, while PVDF-0.20WS2 showed a slightly higher increase in Zeff at energies of 0.662 and 1.333 MeV. PVDF-0.20WC has demonstrated the highest ΣR value, indicating effective shielding against fast neutrons, while PVDF-0.20WS2 had the lowest ΣR value. The Monte Carlo N-Particle Transport version 5 (MCNP5) simulations showed that PVDF-xWC attenuates gamma radiation more than pure PVDF, significantly decreasing the dose equivalent rate. Conclusion: Overall, this research provides insights into the radiation shielding properties of PVDF mixtures, with PVDF-xWC showing the most promising results.

Fabrication of High Power InGaAs Diode Lasers (고출력 InGaAs레이저 다이오드 제작)

  • 계용찬;손낙진;권오대
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.10
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    • pp.79-86
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    • 1994
  • Gain-guided broad-area single quantum well separate confinement heterostructure diode lasers have been fabricated from structures grown by metal organic vapor phase epitaxy. The active layer of the epi-structure is InGaAs emitting 962-965nm and the guiding layer GaAs. The channel width is fixed to 150${\mu}$m and the cavity length varys within the range of 300~800${\mu}$m. For uncoated LD's, the output power of 0.7W has been obtaained at a pulsed current level of 2A, which results about 60% external quantum efficiency. The threshold current density is 200A/cm$^{2}$ for the cavity lengths of 800.mu.m LD's. The stain effect upon the transparent current density has been observed. The internal quantum efficiency is expected to be 88% and the internal loss to be 18$cm^{-1}$. The beam divergence has been measured to be 7$^{\circ}$to lateral and 40$^{\circ}$to transverse direction. finally, 1.2W continuous-wave output power has been obtained at a current level of 2A for AR/HR coated LD's die-bonded on Cu heat-sink and cooled by TEC.

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