• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.420-420
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• 2012

ZnO seed layer were deposited on quartz substrate by sol-gel method and prism-like Al-doped ZnO nanorods (AZO nanorods) were grown on ZnO seed layer by hydrothermal method with various Al concentration ranging from 0 to 2.0 at.%. Structural and optical properties of the AZO nanorods were investigated by field-emission scanning electron microscopy (FE-SEM), X-ray diffraction (XRD), photoluminescence (PL). The diameter of the AZO nanorods was smaller than undoped ZnO nanorods and its diameter of the AZO nanorods decreased with increasing Al concentration. In XRD spectrum, it was observed that stress and full width at half maximum (FWHM) of the AZO nanorods decreased and the 'c' lattice constant increased as the Al concentration increased. From undoped ZnO nanorods, it was observed that the green-red emission peak of deep-level emission (DLE) in PL spectra. However, after Al doping, not only a broad green emission peak but also a blue emission peak of DLE were observed.

• Korean Journal of Materials Research
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• v.4 no.1
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• pp.81-89
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• 1994

Ti film of lOnm thickness and Co film of 18nm thickness were sequentially e-heam evaporated onto Si (100) substrates. Metal deposited samples were rapidly thermal-annt.aled(KTA) in thr N1 en vironment a t $900^{\circ}C$ for 20 sec. to induce the reversal of metal bilayer, so that $CoSi_{2}$ thin films could be formed. The sheet resistance measured by the 4-point probe was 3.9 $\Omega /\square$This valur was maintained with increase in annealing time upto 150 seconds, showing high thermal stab~lity. Thc XRII spectra idrn tified the silicide film formed on the Si substrate as a $CoSi_{2}$ epitaxial layer. The SKM microgr;iphs showed smooth surface, and the cross-sectional TKM pictures revealed that the layer formed on the Si substrate were composed of two Co-Ti-Si alloy layers and 70nm thick $CoSi_{2}$ epl-layer. The AES analysis indicated that the native oxide on Si subs~rate was removed by TI ar the beginning of the RTA, and Ihcn that Co diffused to clean surface of Si substrate so that epitaxial $CoSi_{2}$ film could bt, formed. In thc rasp of KTA at $700^{\circ}C$. 20sec. followed by $900^{\circ}C$, 20sec., the thin film showed lower sheet resistance, but rough surface and interface owing to $CoSi_{2}$ crystal growth. The application scheme of this $CoSi_{2}$ epilayer to VLSI devices and the thermodynarnic/kinetic mechan~sms of the $CoSi_{2}$ epi-layer formation through the reversal of Co/Ti bdayer were discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.13-19
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• 2001

We report on the fabrication and characterization of $Al_{0.3}Ga_{0.7}N$ HFETs with different barrier layer thickness which were grown using plasma-assisted molecular beam epitaxy (PAMBE). The barrier thickness of $Al_{0.3}Ga_{0.7}N$/GaN HFETs could be optimized in order to maximize 2 dimensional electron gas induced by piezoelectric effect without the relaxation of $Al_{0.3}Ga_{0.7}N$ layer. $Al_{0.3}Ga_{0.7}N$/GaN (20 nm/2 mm) HFET with 0.6 ${\mu}m$-long and 34 ${\mu}m$-wide gate shows saturated current density ($V_{gs}=1\;V$) of 1.155 A/mm and transconductance of 250 ms/mm, respectively. From high frequency measurement, the fabricated $Al_{0.3}Ga_{0.7}N$/GaN HFETs showed $F_t=13$ GHz and $F_{max}=48$ GHz, respectively. The uniformity of less than 5% could be obtained over the 2 inch wafer. In addition to the optimization of epi-layer structure, the relation between breakdown voltage and high frequency characteristics has been examined.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.1
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• pp.7-13
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• 2010

We have investigated effects of the rapid thermal annealing of GaN epilayers by molecular beam epitaxy in nitrogen atmosphere. The improvement of structural properties of the samples was observed after rapid thermal annealing under optimum conditions. This improvement in crystal quality is due to a reduction of the spread in the lattice parameter in epilayers. The annealing has been performed in a rapid thermal annealing furnace at $950^{\circ}C$. The effect of rapid thermal annealing on the structural properties of GaN was studied by x-ray diffraction. The Bragg peak shifts toward larger angle as the annealing time increases. As the thermal treatment time increases, FWHM(full width at half maximum) of the peak slightly increase with its decreases followed and it increases again. Results demonstrate that rapid thermal annealing did not always promote qualities of GaN epilayers. However, rapid thermal annealing under optimum conditions improve structural properties of the samples, elevating their crystal quality with a reduction of inaccuracy in the lattice parameter of the epilayers.

• Journal of IKEEE
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• v.20 no.2
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• pp.181-183
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• 2016

In this work, the merged PiN Schottky(MPS) diodes based silicon carbide(SiC) have been optimized and designed for 1200V diodes by 2D-atlas simulation tool. We investigated the optimized characteristics of SiC MPS diodes such as breakdown voltage and specific on-resistance by varying the doping concentrations of P-Grid/epi-layer and space of P-Grid, which are the most important parameters. The breakdown voltage and specific on-resistance, based on Baliga's Figure Of Merit (BFOM), have been compared with and the SiC-based MPS diodes show improved BFOMs with low values of specific on-resistance and high breakdown voltage. It has been demonstrated 1,200 V SiC MPS diodes will find useful applications in high voltage energy-efficient devices.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.47-51
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• 2013

A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.338-338
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• 2010

지난 20여년 동안 반도체 레이저 다이오드는 주로 CD (DVD) 픽업용 (파장: 640 nm 이하) 및 통신용 (파장 1550 nm) 광원 분야에서 집중적으로 개발되어 왔다. 그러나 기술의 개발과 더불어 파장조절이 비교적 자유로워지고 광출력이 증대 되면서 기존의 레이저 고유의 영역까지 그 응용분야기 확대되고 있고, 이에 따라 고출력 반도체 레이저 다이오드의 시장 규모도 꾸준히 증가되고 있는 상황이다. 고출력 반도체 레이저 다이오드는 발진 파장 및 광출력에 따라 다양한 분야에 응용되고 있으며, 특히 발진파장이 808 nm 인 고출력 레이저 다이오드의 경우 재료가공, 펌핑용 광원 (DPSSL, 광섬유 레이저), 의료, 피부미용 (점 제거), 레이저 다이오드 디스플레이 등 가장 다양한 응용분야를 가진 광원 중의 하나라고 할 수 있다. MBE(Molecular Beam Epitaxy)로 성장된 InAlAs 에피층 (epi-layer)을 사용하여 고출력을 갚는 레이저 다이오드를 제작함에 있어서, 에피층은 결함 (defect)이 없는 우수한 단결정이 요구되지만, 실제 결정 성장 과정에서는 성장온도와 Al 조성비 등의 성장 조건의 변화에 따라 전기적 광학적 특성 및 신뢰성에 큰 영향을 받는 것으로 보고되고 있다. 이에 본 연구에서는 DLTS (Deep Level Transient Spectroscopy) 방법을 이용하여 InAlAs 양자점 에피층의 깊은 준위 거동을 조사하였다. DLTS 측정 결과, 0.3eV 부근의 point defect과 0.57 ~ 0.70 eV 영역의 trap이 조사되었으며, 이는 갈륨 (Ga) vacancy와 산소 원자의 복합체에 기인한 결함으로 분석된다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.1
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• pp.51-56
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• 1981

A new I2L process for a high performance I2L structure is proposed. The modifiedstructure consists of a heavily doped extrinsic base and lowly doped intrinsic base where the collector regions are self-alignment with the intrinsic base regions. The proposed process untilizes spin-on sources as the diffusion sources and the self-alignment of collectors is achieved by using the hardened spin-on source as a diffusion mask. Test devices including a 13-stage ring oscillator have been fabricated by the proposed process on n/n+ silicon wafers with 6.5$\mu$m epitaxial layer. The maximum upward current gain of npn transistors is 8 for a three collector I2L cell. The speed-power product and minimum propagation delay for a one collector structure are 3.5 pJ and 50 ns, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.463-463
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• 2010

고휘도 고효율 백색 LED (lighting emitting diode)가 차세대 조명광원으로 급부상하고 있다. 백색 LED를 생산하기 위한 공정에서 MOCVD (유기금속화학증착)장비를 이용한 Epi wafer공정은 에피층과 기판의 격자상수 차이와 열팽창계수차이로 인하여 생성되는 에피결함의 제거를 위하여 기판과 GaN 박막층 사이에 완충작용을 해줄 수 있는 버퍼층 (Buffer layer)을 만들고 그 위에 InGaN/GaN MQW (Multi Quantum Well)공정을 하여 고휘도 고효율 백색 LED를 구현할 수 있다. 이 공정에서 기판의 온도가 불균일해지면 wafer 파장 균일도가 나빠지므로 백색 LED의 yield가 떨어진다. 균일한 기판 온도를 갖기 위한 조건으로 기판과 induction heater의 간격, 가스의 흐름, 기판의 회전, 유도가열코일의 디자인 등이 장비의 설계 요소이다. 코일에 교류전류를 흘려주면 이 코일 안 또는 근처에 있는 도전체에 와전류가 유도되어 가열되는 유도가열 방식은 가열 효율이 높아 경제적이고, 온도에 대한 신속한 응답성으로 인하여 열 손실을 줄일 수 있으며, 출력 온도 제어의 용이성 및 배출 가스 등의 오염 없다는 장점이 있다. 본 연구에서는 유도가열방식의 induction heater를 이용하여 회전에 의한 기판의 온도 균일도 측정을 하였다. 기초 실험으로 저항 가열 히터를 통하여 대류에 의한 온도 균일도를 평가하였다. 그 결과 gap이 3 mm일 때, 평균 온도 $166.5^{\circ}C$ 에서 불균일도 6.5 %를 얻었으며 이를 바탕으로 induction heater와 graphite susceptor의 간격이 3 mm일 때, 회전에 의한 온도 균일도를 측정을 하였다. 가열원은 induction heater (viewtong, VT-180C2)를 사용하였고, 가열된 graphite 표면의 온도를 2차원적으로 평가하기 위하여 적외선 열화상 카메라(Fluke, Ti-10)을 이용하여 온도를 측정하였다. 기판을 회전하면서 표면 온도의 평균과 표준 편차를 측정한 결과 2.5 RPM일 때 평균온도 $163^{\circ}C$ 에서 가장 좋은 5.5 %의 불균일도를 확인할 수 있었고, 이를 상용화 전산 유체 역학 코드인 CFD-ACE+의 모델링 결과와 비교 분석 하였다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.22 no.1
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• pp.5-10
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• 2012

In general, the fabrications of the LEDs with mesa structure are performed grown by MOCVD method. In order to etch and separate each chips, the LEDs are passed the RIE and scribing processes. The RIE process using plasma dry etching occur some problems such as defects, dislocations and the formation of dangling bond in surface result in decline of device characteristic. The SAG method has attracted considerable interest for the growth of high quality GaN epi layer on the sapphire substrate. In this paper, the SAG method was introduced for simplification and fabrication of the high quality epi layer. And we report that the size of selective area do not affect the characteristics of original LED. The diameter of SAG circle patterns were choose as 2500, 1000, 350, and 200 ${\mu}m$. The SAG-LEDs were measured to obtain the device characteristics using by SEM, EL and I-V. The main emission peaks of 2500, 1000, 350, and 200 ${\mu}m$ were 485, 480, 450, and 445 nm respectively. The chips of 350, 200 ${\mu}m$ diameter were observed non-uniform surface and resistance was higher than original LED, however, the chips of 2500, 1000 ${\mu}m$ diameter had uniform surface and current-voltage characteristics were better than small sizes. Therefore, we suggest that the suitable diameter which do not affect the characteristic of original LED is more than 1000 ${\mu}m$.