• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.1
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• pp.17-24
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• 2024

In this paper, we propose a highly secure technique to hide confidential data in image pixels using a quadruple encryption techniques. In the proposed technique, the boundary surface where the image outline exists and the flat surface with little change in pixel values are investigated. At the boundary of the image, in order to preserve the characteristics of the boundary, one bit of confidential data that has been multiply encrypted is spatially encrypted again in the LSB of the pixel located at the boundary to hide the confidential data. At the boundary of an image, in order to preserve the characteristics of the boundary, one bit of confidential data that is multiplely encrypted is hidden in the LSB of the pixel located at the boundary by spatially encrypting it. In pixels that are not on the border of the image but on a flat surface with little change in pixel value, 2-bit confidential data that is multiply encrypted is hidden in the lower 2 bits of the pixel using location-based encryption and spatial encryption techniques. When applying the proposed technique to hide confidential data, the image quality of the stego-image is up to 49.64dB, and the amount of confidential data hidden increases by up to 92.2% compared to the existing LSB method. Without an encryption key, the encrypted confidential data hidden in the stego-image cannot be extracted, and even if extracted, it cannot be decrypted, so the security of the confidential data hidden in the stego-image is maintained very strongly. The proposed technique can be effectively used to hide copyright information in general commercial images such as webtoons that do not require the use of reversible data hiding techniques.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.281-284
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• 2005

Kerberos is system that offer authorization in internet and authentication service. Can speak that put each server between client and user in distributed environment and is security system of symmetry height encryption base that offer authentication base mutually. Kerberos authentication is based entirely on the knowledge of passwords that are stored on the Kerberos Server. A user proves her identity to the Kerberos Server by demonstrating Knowledge of the key. The fact that the Kerberos Server has access to the user's decrypted password is a rwsult of the fact that Kerberos does not use public key cryptogrphy. It is a serious disadvantage of the Kerbercs System. The Server must be physically secure to prevent an attacker from stealing the Kerberos Server and learning all of the user passwords. Kerberos was designend so that the server can be stateless. The Kerberos Server simply answers requests from users and issues tickets. This study focused on designing a SIP procy for interworking with AAA server with respect to user authentication and Kerberos System. Kerberos is security system of encryption base that offer certification function mutually between client application element and server application element in distributed network environment. Kerberos provides service necessary to control whether is going to approve also so that certain client may access to certain server. This paper does Credit-Control Server's function in AAA system of Diameter base so that can include Accounting information that is connected to Rating inside certification information message in Rating process with Kerberos system.

• Journal of Korea Multimedia Society
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• v.8 no.11
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• pp.1520-1530
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• 2005

As XML is recognized as a prevalent standard for document representation and exchange in the Internet, the need for security of XML becomes very important issue. Until now researches on XML security have been focused on confidentiality or integrity like encryption and digital signature technology. But, as XML data becomes more massive and complicated, it requires managerial security that decided access permit or deny by the authority oi user who is using the XML data. Thus it requires models and mechanisms enabling the specification and enforcement of access control policies for XML documents. In this paper, we suggest the new access control model and mechanism that separate XML documents by access level, assign roles to each user by applying Role Based Access Control (RBAC) and perform access control to specific documents by encrypting each section with roles. The method, we suggested, has an advantage that it does not need to update the whole keys used in encryption process by updating only the relations between appropriate secure layers.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.67-74
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• 2004

AES is frequently used as a symmetric cryptography algorithm for the Internet. Wireless embedded systems increasingly use more conventional wired network protocols. Hence, it is important to have low-cost implementations of AES for thor The basic architecture of AES unrolls oかy one full cipher round which uses 20 S-boxes together with the key scheduler and the algorithm repeatedly executes it. To reduce the implementation cost further, the folded architecture which uses only eight S-box units was studied in the recent years. In this paper, we will study a low-cost AES implementation for wireless communication technology based on the folded architecture. We first improve the folded architecture to avoid the sixteen bytes of additional state memory. Then, we implemented a single byte architecture where only one S-box unit is used for data encryption and key scheduling. It takes 352 clocks to finish a complete encryption. We found that the maximum clock frequency of its FPGA implementation reaches about 40 MHz. It can achieve about 13 Mbps which is enough for 3G wireless communication technology.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.5
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• pp.1938-1962
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• 2015

Security of information during transmission is a major issue in this modern era. All of the communicating bodies want confidentiality, integrity, and authenticity of their secret information. Researchers have presented various schemes to cope with these Internet security issues. In this context, both steganography and cryptography can be used effectively. However, major limitation in the existing steganographic methods is the low-quality output stego images, which consequently results in the lack of security. To cope with these issues, we present an efficient method for RGB images based on gray level modification (GLM) and multi-level encryption (MLE). The secret key and secret data is encrypted using MLE algorithm before mapping it to the grey-levels of the cover image. Then, a transposition function is applied on cover image prior to data hiding. The usage of transpose, secret key, MLE, and GLM adds four different levels of security to the proposed algorithm, making it very difficult for a malicious user to extract the original secret information. The proposed method is evaluated both quantitatively and qualitatively. The experimental results, compared with several state-of-the-art algorithms, show that the proposed algorithm not only enhances the quality of stego images but also provides multiple levels of security, which can significantly misguide image steganalysis and makes the attack on this algorithm more challenging.

• Korean Journal of Optics and Photonics
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• v.14 no.6
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• pp.636-642
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• 2003

We proposed the optical system using two divided halftone images to hide the original image and a joint transform correlator. The encryption procedure is performed by the Fourier transform of the product of each divided image by visual cryptography and the same random image which is generated by computer processing. As a result, we can obtain two Fourier divided images which are used as the encrypted image and the decrypting key, respectively. In the decryption procedure, both the encrypted image and the decrypting key are located on the joint input plane. Then the original image is reconstructed on a CCD camera which is located in the output plane. An autocorrelation term of joint transform correlator contributes to decrypt the original image. To demonstrate the efficiency of the proposed system, computer simulations and noise analysis are performed. The result show that the proposed system is a very useful optical certification system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.875-880
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• 2019

A RC4 stream cipher is widely used for security applications such as IEEE 802.11 WEP, IEEE 802.11i TKIP and so on, because it can be simply implemented to dedicated circuits and achieve a high-speed encryption. RC4 is also used for systems with limited resources like IoT, but there are performance limitations. RC4 consists of two stages, KSA and PRGA. KSA performs initialization and randomization of S-box and K-box and PRGA produces cipher texts using the randomized S-box. In this paper, we initialize the S-box and K-box in the randomization of the KSA stage to reduce the initialization delay. In the randomization, we use clusters to process swap operation between elements of S-box in parallel and can generate two cipher texts per clock. The proposed RC4 cipher hardware can initialize S-box and K-box without any delay and achieves about 2 times to 6 times improvement in KSA randomization and key stream generation.

• Journal of IKEEE
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• v.25 no.1
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• pp.88-94
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• 2021

Public-key cryptographic algorithms such as RSA and ECC, which are currently in use, have used mathematical problems that would take a long time to calculate with current computers for encryption. But those algorithms can be easily broken by the Shor algorithm using the quantum computer. Lattice-based cryptography is proposed as new public-key encryption for the post-quantum era. This cryptographic algorithm is performed in the Polynomial Ring, and polynomial multiplication requires the most processing time. Therefore, a hardware model module is needed to calculate polynomial multiplication faster. Number Theoretic Transform, which called NTT, is the FFT performed in the finite field. The logic verification was performed using HDL, and the proposed design at the transistor level using Hspice was compared and analyzed to see how much improvement in delay time and power consumption was achieved. In the proposed design, the average delay was improved by 30% and the power consumption was reduced by more than 8%.