• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.3C
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• pp.293-298
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• 2008

Recently, with the development of mobile techniques and the consideration to conveniency of using, the research on Mobile RFID Reader technique is getting more and more attentions. Until now, all security authentication algorithms of RFID are algorithms about range between Tag and Reader. The range between Reader and backend DB is composed by wired networks, so it's supposed to be secure range. But it must be taken account of the problem of information security and privacy in wireless range during the design of Mobile RFID Reader. In this paper we design an blind signature scheme based on weil-paring finite group's ECC encryption scheme, and by using this blind signature we propose the anonymous authorization scheme to Mobile RFID Reader's users.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.204-214
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• 1999

The user authentication service can be used to prevent telecommunications piracy and to demand reliable payment from subscriber. Over the last few years several of the cryptographic systems being used by the IS-41 North American Mobile telephones have been broken. These algorithms included ORYX, CMEA and CAVE. The process of replacing these algorithms is already underway. In this paper we designed a hash function and applied it to the authentication algorithm of IS-95A authentication system. We also analyzed the randomness properties of designed algorithm using statistical analysis and simulated the validity of this algorithm using C programming language.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.199-202
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• 2003

IPsec is a standardization way for protection of IP packets in network layer and it is composed of three protocols that is AH(Authentication Header), ESP(Encapsulation Security Protocol) and IKE(Internet Key Exchange). Before doing encryption and decryption using AH or ESP protocols, both of communicating entities have to share same key safely. IKE protocol works automatically. But it has less interoperability because IKE protocol is not simple. A work which standardize IKEv2 has been done up to now. In this article, we will examine the Cryptographic Algorithms of IKEv2, and describe the AES usage with IPsec, based on the IETF Draft document.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.6
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• pp.937-942
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• 2002

The use of digital imaging technique and digital contents based on internet has grown rapidly for last several years, and the needs of digital image protection become more important. For the purpose of copyright protection on digital image, the verification of authentication techniques like content authentication, ownership authentication, illegal copy and etc are needed. Digital watermarking, the invisible encryption technique to insert digital watermark into image the sophisticated perceptual information should be used for providing transparency and robustness of images on watermarking process. In this paper, we implement the algorithm for preventing forged attack, ownership protection and authentication by transforming the wavelet algorithms in frequency domain in terms of human visual system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.3
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• pp.1691-1699
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• 2014

IEEE developing WAVE specifications are able to support V2V and V2I wireless communications, and these functionalities can be used to enhance vehicle operational safety. To overcome any security weaknesses that are inherent in wireless communications, WAVE specification should support message encryption and authentication functions. In this study, we have implemented WAVE security algorithms in IEEE P1609.2 with openssl library and C language. We have verified the normal operation of implemented software, using the test vectors of related specifications, and measured their performance. Our software is platform independent, and can be used for the full implementation of WAVE specification.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.9
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• pp.3266-3285
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• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

• Journal of Korea Multimedia Society
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• v.10 no.5
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• pp.668-678
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• 2007

The development of a wire and wireless communication technologies might permit easily accessing on various information. But, the easiness of accessing information has basically the problem of an unintended information outflow. An executable file which has key algorithms, data and resources for itself has very weak point in the security. Because the various information such as algorithms, data and resources is included in an executable file on embedded systems or virtual machines, the information outflow problem may appear more seriously. In this paper, we propose a technique which can be protecting the executable file contents for resolving the outflow problem through the encryption. Experimentally, we applied the proposed technique to EVM-the virtual machine for embedded system and verified it. Also, we tried a benchmark test for the proposed technique and obtained reasonable performance overhead.

• International Journal of Computer Science & Network Security
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• v.24 no.1
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• pp.61-70
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• 2024

Cloud Computing is internet-based computing, where the users are provided with whatever service they need from the resources, software, and information. Recently, the security of cloud computing is considered as one of the major issues for both cloud service providers CSP and end-users. Privacy and highly confidential data make many users refuse to store their data within cloud computing, since data on cloud computing is not dully secured. The cryptographic algorithm is a technique which is used to maintain the security and privacy of the data on the cloud. In this research, we applied eight different cryptographic algorithms on Xen and KVM as hypervisors on cloud computing, to be able to measure and compare the performance of the two hypervisors. Response time and CPU utilization while encryption and decryption have been our aspects to measure the performance. In terms of response time and CPU utilization, results show that KVM is more efficient than Xen on average at 11.5% and 11% respectively. While TripleDES cryptographic algorithm shows a more efficient time response at Xen hypervisor than KVM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.