• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2789-2800
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• 1996

Real time fractal coding for successive QCIF 144*176 luminance images has been implemented on a 50MHz IBM 486 personal computer. To satisfy the frame encoding speed and data compression ratio, following algorithms are adopted. In order to minimize encoding time, extension SAS being not searching of domain blocks is used. for reducing the bits per pixel, conventioal 4*4 range block is extended to 8*8 range block. and range block extension decrease quality of decoded image. For improvement quality of decoded image, the paper apply quad-tree partition mothod. In order to divide **8 range block, self-simiarity is compared 8*8 range block with spatial contractive transformed 8*8 domain block. According to self-simiarity, the block is partitioned and owing to block partition, increased encoding time is minimized. According to self-simiarity of 8*8 range block and spatial contractive transformed 8*8 domain block, number of fractal factor is varied. Simultaneously with minimizing the decrement of decoded image's quality, transmittion rate and encoding time is shorted. The results enable us to process the real-time fractal coding. For the claire test image, the average PSNR was 32.4dB, 0.12 bit rates and 33ms coding time per frame.

• Journal of Korea Multimedia Society
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• v.22 no.2
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• pp.186-193
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• 2019

Visible light communication technology is being studied and developed in various ways due to advantages such as high transmission speed, excellent positioning and higher security. However, existing visible light communication systems have difficulties in entering the market because they use special transmitters and receivers. We will overcome the difficulty if we develope a VLC system that uses a conventional LED light as a transmitter and a smartphone camera as a receiver. What matters is that LED lights include a scatter filter to prevent glareness for human eyes, but the existing VLC(Visual Light Communication) method can not be applied. In this paper, we propose a method to encode data with On / Off patterns of LEDs in the lighting with $M{\times}N$ LEDs. We defined parameters like L-off-able and K-seperated to facilitate the recognition of On / Off patterns in the diffused Lights. We conducted experiments using an LED lighting and smart phones to determine the parameter values. Also, the maximum transmission rate of our encoding technique is mathematically presented. Our encoding scheme can be applied to indoor and outdoor positioning applications or settlement of commercial transactions.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.857-860
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• 1991

This paper describes a High-Speed 8-bit Current-Mode BiCMOS A/D Converter. The characteristics of this A/D Converter are as fellows. First, as ADC is operating in current-mode we can obtain the properties of increase of converting speed, low noise, and wideband. Second, the properties of high switching speed in bipolar transistor and of high packing density, low power consumption in MOS trnsistor are combined. Finally we reduce chip area by designing it with subranging mode and improve the converting speed by performing subtraction directly, which doesn't need D/A convertings, using current switching element. This converter is composed of two 4-bit ADC, current soure array which provides signal and reference current, current comparator and encoding network.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2001.11a
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• pp.335-354
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• 2001

.Next Generation Multimedia Streaming Technology Massive Scale Support $\rightarrow$ Clustered Solution Adaptive to Heterogeneous Network daptive to Heterogeneous Terminal Capability Presentation Technique .SMART Server Architecture .HERMES File System .Clustered Solution . High Speed Storage Interconnect .' Content Partitioning . Load Management . Support for Heterogeniety . Adaptive End to End Streaming Transport: Unicast vs. Multicast '. Scalable Encoding

• The KIPS Transactions:PartB
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• v.9B no.6
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• pp.715-726
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• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.6
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• pp.492-505
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• 2022

This study is a study on the results of improving the logic to effectively transmit and decode compressed data in real time by improving the encoding and decoding performance of BL-beta codes that can be used for lossless real-time transmission of IoT sensing data. The encoding process of BL-beta code includes log function, exponential function, division and square root operation, etc., which have relatively high computational burden. To improve them, using bit operation, binary number pattern analysis, and initial value setting of Newton-Raphson method using bit pattern, a new regularity that can quickly encode and decode data into BL-beta code was discovered, and by applying this, the encoding speed of the algorithm was improved by an average of 24.8% and the decoding speed by an average of 5.3% compared to previous study.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.275-280
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• 2010

In this paper, we discuss and propose an efficiently parallelized block cipher algorithm on the CELL BE processor. With considering the heterogeneous feature of the CELL BE architecture, we apply different encoding/decoding methods to PPE and SPE and improve the throughput. Our implementation was fully tested, with execution results showing achievement of high throughput, capable of supporting as high network speed as 2.59 Gbps. Compared to various parallel implementations on multi-core systems, our approach provides speedup of 1.34 in terms of encoding/decoding speed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.10
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• pp.1868-1871
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• 2007

This paper proposes a novel scheme to significantly reduce mode decision time by predicting optimal mode candidates. Unlike previous fast mode decision algorithms computing RDcost in a pre-defined mode order, the proposed scheme predicts optimal mode candidates and calculates their RDcosts first, increasing the possibility to satisfy early-exit conditions sooner, resulting in fast mode decision. This H.264 mode decision time reduction enables small computing power mobile devices to handle H.264 encoding effectively. Extensive simulations show that, when compared with JM10.2, AMD and LCIMS, the proposed scheme boosts H.264 encoding speed by up to 575% with a reasonable image quality degradation.