• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.63-69
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• 2011

In this paper, we propose a fixed-complexity sphere encoder (FSE) for multi-user multi-input multi-output (MU-MIMO) systems. The proposed FSE accomplishes a scalable tradeoff between performance and complexity. Also, because it has a parallel tree-search structure, the proposed encoder can be easily pipelined, leading to a tremendous reduction in the precoding latency. The complexity of the proposed encoder is also analyzed, and we propose two techniques that reduce it. Simulation and analytical results demonstrate that in a $4{\times}4$ MU-MIMO system, the proposed FSE requires only 11.5% of the computational complexity needed by the conventional QR decomposition with M-algorithm encoder (QRDM-E). Also, the encoding throughput of the proposed encoder is 7.5 times that of the QRDM-E with tolerable degradation in the BER performance, while achieving the optimum diversity order.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2467-2470
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• 2003

This paper presents a new structure of MPEG-4 AAC encoder. The proposed encoder directly shapes quantization noise distribution according to the energy distribution curve and thereafter performs adjustment of the offset level of the noise distribution to meet the given bit rate. The direct noise shaping and the bit rate matching scheme of the proposed encoder algorithm significantly alleviate the problem of conventional encoder's processing burden related with the employment of the precise psychoacoustic model and iteration intensive quantizer. The encoder algorithm is implemented on ARM processor with fixed-feint arithmetic operations. The audio quality of the implemented system is observed comparable to those of commercially available encoders, white the complexity of the implementation is drastically reduced in comparison to the conventional encoder systems.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.5
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• pp.1035-1040
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• 2009

We propose a new encoder/decoders based on an tune able wavelength converter(TWC) and an arrayed waveguide grating(AWG) router for large capacity optical CDMA networks. The proposed encoder/decoder treats codewords of wavelength/time 2-D code simultaneously using the dynamic code allocation property of the TWC and the cyclic property of the AWG router, and multiple subscribers can share the encoder/decoder in networks. Feasibility of the structure of the proposed encoder/decoder for dynamic code allocation is tested through simulations using two wavelength/time 2-D codes, which are the generalized multi-wavelength prime code(GMWPC) and the generalized multi-wavelength Reed-Solomon code(GMWRSC). Test results show that the proposed encoder/decoder can increase the channel efficiency not only by increasing the number of simultaneous users without any multiple-access interference but by using a relatively short length CDMA codes.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1183-1190
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.452-459
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• 2019

In this paper, we describe a PCM encoder structure that can update the telemetry system parameters in real time. In the PCM encoder, an analog signal control unit for FPGA, flash memory, and sensor data acquisition was constructed. UART communication, analog signal control, flash memory control, and frame generation are possible through logic inside FPGA of PCM encoder. UART communication allows the PC to transmit parameter data to the PCM encoder, and flash memory is controlled to update the parameter of the telemetry system in real time and finally the frame is formed. Simulation and verification were performed to confirm whether the parameter data is updated in real time, and the proposed structure was used to construct a telemetry system with enhanced flexibility and convenience.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.325-343
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• 2012

This paper proposes the coding method to predict the split structure of LCU in the current frame on the basis of the reference frame or temporally-previous frame. HEVC encoder determines split structure according to image characteristics in LCU which is an basic element of CU. The split structure of the current LCU is very similar to the split structure of collocated LCU in the reference frame or temporally-previous frame. Thus, this paper proposes the method to reduce the encoder computational complexity by predicting split structure of the current LCU on the basis of that of collocated LCU in the reference frame or temporally-previous frame. And it also proposes the method to reduce the BD-Bitrate by coding after the prediction of the CU split information. The simulation results of changing only encoder showed that the mean of encoder computational complexity was lower by 21.3%, the decoder computational complexity was negligible change and the BD-Bitrate increase by the maximum of 0.6%. Also, the method changing encoder, bitstream, and decoder improves the mean of encoder computational complexity was lower by 22%, the decoder computational complexity was negligible change and the BD-Bitrate is improved to the maximum of 0.3%. When compared with the conventional method, indicating that the proposed method is superior.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.1-4
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• 2001

SRM(Switched Reluctance Motor) uses reluctance torque by pulse excitation control. SRM drives are much studied in electrical vehicles and industrial application due to the simple, robust mechanical structure and high speed characteristics. For the high performance control of SRM, it is necessary to synchronize the stator phase excitation with the rotor position. This paper proposes a new encoder for high performance excitation control of SRM. The proposed encoder has complex structures of incremental and absolute encoder. An each phase inductance profile can be synchronized with 4-bit absolute position signal and incremental pulses are used for speed detection. Low cost and simple manufacturing of SRM encoder is possible.

• The Journal of Korea Robotics Society
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• v.14 no.1
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• pp.8-13
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• 2019

Visual place recognition is widely researched area in robotics, as it is one of the elemental requirements for autonomous navigation, simultaneous localization and mapping for mobile robots. However, place recognition in changing environment is a challenging problem since a same place look different according to the time, weather, and seasons. This paper presents a feature extraction method using a deep convolutional auto-encoder to recognize places under severe appearance changes. Given database and query image sequences from different environments, the convolutional auto-encoder is trained to predict the images of the desired environment. The training process is performed by minimizing the loss function between the predicted image and the desired image. After finishing the training process, the encoding part of the structure transforms an input image to a low dimensional latent representation, and it can be used as a condition-invariant feature for recognizing places in changing environment. Experiments were conducted to prove the effective of the proposed method, and the results showed that our method outperformed than existing methods.