• Earthquakes and Structures
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• v.5 no.2
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• pp.161-205
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• 2013

We study seismically induced, anti-plane strain wave motion in a non-homogeneous geological region containing tunnels. Two different scenarios are considered: (a) The first models two tunnels in a finite geological region embedded within a laterally inhomogeneous, layered geological profile containing a seismic source. For this case, labelled as the first boundary-value problem (BVP 1), an efficient hybrid technique comprising the finite difference method (FDM) and the boundary element method (BEM) is developed and applied. Since the later method is based on the frequency-dependent fundamental solution of elastodynamics, the hybrid technique is defined in the frequency domain. Then, an inverse fast Fourier transformation (FFT) is used to recover time histories; (b) The second models a finite region with two tunnels, is embedded in a homogeneous half-plane, and is subjected to incident, time-harmonic SH-waves. This case, labelled as the second boundary-value problem (BVP 2), considers complex soil properties such as anisotropy, continuous inhomogeneity and poroelasticity. The computational approach is now the BEM alone, since solution of the surrounding half plane by the FDM is unnecessary. In sum, the hybrid FDM-BEM technique is able to quantify dependence of the signals that develop at the free surface to the following key parameters: seismic source properties and heterogeneous structure of the wave path (the FDM component) and near-surface geological deposits containing discontinuities in the form of tunnels (the BEM component). Finally, the hybrid technique is used for evaluating the seismic wave field that develops within a key geological cross-section of the Metro construction project in Thessaloniki, Greece, which includes the important Roman-era historical monument of Rotunda dating from the 3rd century A.D.

• Korean Journal of Construction Engineering and Management
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• v.13 no.6
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• pp.24-32
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• 2012

Reinforced Concrete is the most dominant structure type for buildings in South Korea. Reinforced Concrete is one of materials having the most cost and quantity at construction projects. It is important to manage concrete quantity so that the total project cost is not affected due to underestimate or overestimate of its quantity. Generally the concrete quantity is taken-off based on the volume of the space inside forms without subtracting volumes of rebar embedded, which cannot be considered to make quite accurate results. Resource waste and extra cost due to over or under estimate of quantity occur since they cannot estimate accurate quantity at practices. Therefore, the objective of this paper is to analyze the effect of the volume for rebars embedded in reinforced concrete members. By comparing the quantity based on the existing method with the one from BIM data, it was found that about 1~2% of quantity discrepancy was observed while the typical concrete waste rate is 1 % at the current practice.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.6
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• pp.359-368
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• 2017

As the BadUSB is a vulnerability, in which a hacker tampers the firmware area of a USB flash drive. When the BadUSB device is plugged into the USB port of a host system, a malicious code acts automatically. The host system misunderstands the act of the malicious behavior as an normal behaviour for booting the USB device, so it is hard to detect the malicious code. Also, an antivirus software can't detect the tampered firmware because it inspects not the firmware area but the storage area. Because a lot of computer peripherals (such as USB flash drive, keyboard) are connected to host system with the USB protocols, the vulnerability has a negative ripple effect. However, the countermeasure against the vulnerability is not known now. In this paper, we analyze the tampered area of the firmware when a normal USB device is changed to the BadUSB device and propose the countermeasure to verify the integrity of the area when the USB boots. The proposed method consists of two procedures. The first procedure is to verify the integrity of the area which should be fixed even if the firmware is updated. The verification method use hashes, and the target area includes descriptors. The second procedure is to verify the integrity of the changeable area when the firmware is updated. The verification method use code signing, and the target area includes the function area of the firmware. We also propose the update protocol for the proposed structure and verify it to be true through simulation.

• Journal of the Korean Society for Nondestructive Testing
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• v.20 no.4
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• pp.285-289
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• 2000

This study suggests a rebar detection technique for simultaneous detection of size and cover of embedded reinforcement in concrete. The structure of the probe made in this study is somewhat different from commercial ones. This probe has three sensing coils. Rebar size and cover depth can be evaluated by detecting and analyzing the signal from them. Amplitude and phase variation of each coil in the probe was investigated using an impedance analyzer and the loci of transfer functions of the coils were analyzed. The locus of transfer function from the sensing coil positioned inside excitation coil was simple as well known, but the others from the coils outside excitation coil were not so. Actual experiment on rebar detection was performed with our probe and an eddy current test system for various rebar sizes and depths. The signal shape according to variation of cover depths showed the same tendency with the transfer function loci acquired by impedance analyzer. The different variation pattern of signal enabled to evaluate rebar size and cover depth simultaneously.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.489-498
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• 2004

VLIW processor is considered to be an appropriate processor for the embedded system, provided with high performance and low power con-sumption due to its simple hardware structure. Unfortunately, the VLIW processor often suffers from high memory access latency due to the variable length of I-packets, which consist of independent instructions to be issued in parallel. It is because of the variable I-packet length that some I-packets must be placed over two cache blocks, which are called straddle I-packets, so that two cache accesses are required to fetch such I-packets. In this paper, an expansion buffer cache is proposed to improve not only the instruction fetch bandwidth, but also the power consumption of the I-cache with moderate hardware cost. The expansion buffer cache has a small expansion buffer containing a fraction of a straddle packet along with the main cache to reduce the additional cache accesses due to the straddle I-packets. With a great reduction in the cache accesses due to the straddle packets, the expansion buffer cache can achieve $5{\~}9{\%}$improvement over the conventional I-caches in the $Delay{\cdot}Power{\cdot}Area$ metric.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.311-311
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• 2013

The resistance switching memory devices have several advantages to take breakthrough for the limitation of operation speed, retention, and device scale. Especially, the metal-oxide materials such as ZnO are able to fabricate on the flexible and visible transparent plastic substrate. Also, the quantum dots (QDs) embedded in dielectric layer could be improve the ratio between the low and the high resistance becauseof their Coulomb blockade, carrier trap and induced filament path formation. In this study, we irradiated 0.2-MeV-electron beam on the ZnO/QDs/ZnO structure to control the defect and oxygen vacancy of ZnO layer. The metal-oxide QDs embedded in ZnO layer on Pt/glass substrate were fabricated for a memory device and evaluated electrical properties after 0.2-MeV-electron beam irradiations. To formation bottom electrode, the Pt layer (200 nm) was deposited on the glass substrate by direct current sputter. The ZnO layer (100 nm) was deposited by ultra-high vacuum radio frequency sputter at base pressure $1{\times}10^{-10}$ Torr. And then, the metal-oxide QDs on the ZnO layer were created by thermal annealing. Finally, the ZnO layer (100 nm) also was deposited by ultra-high vacuum sputter. Before the formation top electrode, 0.2 MeV liner accelerated electron beams with flux of $1{\times}10^{13}$ and $10^{14}$ electrons/$cm^2$ were irradiated. We will discuss the electrical properties and the physical relationships among the irradiation condition, the dislocation density and mechanism of resistive switching in the hybrid memory device.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.8
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• pp.133-140
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• 2002

In this paper, the structure of integrated navigation computer for experiment is proposed. It is designed for considering the real time processing and data storage capacity. It will be used in missile, aircraft, submarine system and experimental vehicle. The I/O device supports IMU, GPS, odometer, altimeter, depth sensor, inclinometer etc. And the main storage device uses the tape device. That can improve the system stability. Therefore it can be used in a high dynamic or shock environment. The embedded linux is used as an Operating System. For the real time capability, sensor data processing and algorithm processing units are seperated. The time synchronization is referenced by IMU data.

• Journal of Korea Multimedia Society
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• v.15 no.10
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• pp.1247-1256
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• 2012

There are many filter based image processing algorithms and they usually require a huge amount of computations and memory accesses making it hard to attain a real-time performance, expecially in embedded applications. In this paper, we propose a pipelined hardware structure of the filter based face detection algorithm to show that the real time performance can be achieved by hardware design. In our design, the whole computation is divided into three pipeline stages: resizing the image (Resize), Transforming the image (ICT), and finding candidate area (Find Candidate). Each stage is optimized by considering the parallelism of the computation to reduce the number of cycles and utilizing the line memory to minimize the memory accesses. The resulting hardware uses 507 KB internal SRAM and occupies 9,039 LUTs when synthesized and configured on Xilinx Virtex5LX330 FPGA. It can operate at maximum 165MHz clock, giving the performance of 108 frame/sec, while detecting up to 20 faces.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1076-1087
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• 2010

Together with a new advent of embedded processor developed to support specific application area and it evolution, a new research of software development to support the embedded processor and its commercial challenge has been revitalized. Retargetability is typically achieved by providing target machine information, ADL, as input. The ADLs are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, assembler, profiler, and debugger. The EXPRESSION ADL follows a mixed level approach-it can capture both the structure and behavior supporting a natural specification of the programmable architectures consisting of processor cores, coprocessors, and memories. And it was originally designed to capture processor/memory architectures and generate software toolkit to enable compiler-in-the-loop exploration of SoC architecture. In this paper, we designed the class-based ADL based on the EXPRESSION ADL to promote the write-ability, extensibility and verified the validation of grammar. For this works, we defined 6 core classes and generated the EXPRESSION's compiler and simulator through the MIPS R4000 description.