• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1308-1311
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• 2002

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in wireless multimedia applications. The discussion will focus on the architectural design techniques for implementing a high-performance video compression/decompression chip at low power architectures. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz for 128k∼144kbps. By introducing the efficiently optimized Frame Memory Interface architecture, low power motion estimation and embedded ARM microprocessor and AMBA interface, the proposed MPEG-4 video codec has low power consumption for wireless multimedia applications such as IMT-2000.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.241-244
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• 2003

Nowadays image processing is very useful for some field of traffic applications. The one reason is we can construct the system in a low price, the other is the improvement of hardware processing power, it can be more fast to processing the data. In this study, I propose the traffic monitoring system that implement on the embedded system environment. The whole system consists of two main part, one is host controller board, the other is image processing board. The part of host controller board take charge of control the total system, interface of external environment. and OSD(On screen display). The part of image processing board takes charge of image input and output using video encoder and decoder, image classification and memory control of using FPGA, control of mouse signal. And finally, fer stable operation of host controller board, uC/OS-II operating system is ported on the board.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.1399-1404
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• 1990

There is an increasing need to apply artificial intelligence to the real application fields of industry. These include an intelligent process control, an expert machine and a diagnostic and/or maintenance machine. These applications are implemented in AI Languages. It is commonly recognized that AI Languages, such as Common Lisp or Prolog, require a workstation. This is mainly due to the fact that both languages need a large amount of memory space and disk storage space. Workstations are appropriate for a laboratory or office environment. However, they are too bulky to use in the real application fields of industry or business. Also users who apply artificial intelligence to these fields wish to have their own operating systems. We propose a new design method of an intelligent controller which is embedded within equipment and provides easy-to-use tools for artificial intelligence applications. In this paper we describe the new design method of a VMEbus based intelligent controller for artificial intelligence applications and a small operating system which supports Common Lisp and Prolog.

• 제어로봇시스템학회논문지
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• 제21권5호
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• pp.477-481
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• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.113-116
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• 1999

This paper presents a hardware architecture of AAL(ATM Adaptation Layer) type 2 switch. The proposed architecture can assign and configure maximum AAL2 CID limit. AAL2 is the protocol which has been recommended by ITU-T and ATM-Forum for low bit rate delay sensitive services. The architecture assumes 155 Mbps STM-1/STS-3c physical interface, maximum VCC can be 64K connections. It can support maximum 16,384M AAL2 connections. For efficient use of peripheral memory, a concept of segment address was proposed. The proposed AAL2 switch hardware architecture can be used in ATM network as a standalone server or embedded module in a ATM switching system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.935-938
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• 1999

메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2007년도 춘계학술대회 논문집
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• pp.1735-1740
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• 2007

Communication network in KTX (Korea Train eXpress), the express train system, has to transmit status variables periodically within tens of seconds and real-time control informations which has short reply like status transition or alarm. KTX uses $Tornad^*$ (TOken Ring Network Alsthom Device) network for this purpose. This network can send and receive messages which enable express train applications embedded in intelligence boards to communicate by itself. Layer 1, 2 of $Tornad^*$ is implemented with differential manchester encoding and IEEE 802.4 standard(token bus standard) respectively. To implement layer 1 and 2, we implemented twisted pair modem using FPGA for layer 1 and used MC68824 from Motorola for layer 2. MC68824 bus arbitration and memory controller is implemented using CPLD.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2000년도 추계학술발표논문집 (상)
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• pp.109-112
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• 2000

이동 단말기 관리, 무인 항공 제어 시스템 둥의 시스템에서는 검색 대상의 정보(위치, 여러 가지 상태등)가 시시각각으로 빠르게 변화하므로 현재의 상태를 정확히 파악하기 위하여 많은 양의 자료 검색, 변경 요청이 빈번히 발생한다. 이와 같은 시스템에서의 상태 정보 검색은 자료의 효용성이 사라지기 전에 이루어져야 하므로 디스크 I/O가 많은 디스크 상주형 데이터베이스로는 한계점을 안고 있다. 또한 빠른 검색을 지원할 수 있는 주기억장치 상주형 데이터베이스로는 다량의 데이터를 저장해야 하는 어려움을 안고 있다. 본 논문에서는 위와 같은 실시간 검색 기능과 대용량 자료 저장의 2가지 요구 사항을 만족시키기 위한 내장형 주기억장치 저장 시스템을 개발하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.84-85
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• 2005

Dislocations are often found at Shallow Trench Isolation (STI) process after repeated thermal cycles. The residual stress after STI process often leads defect like dislocation by post STI thermo-mechanical stress. Thermo-mechanical stress induced by STI process is difficult to remove perfectly by plastic deformation at previous thermal cycles. Embedded flash memory process is very weak in terms of post STI thermo-mechanical stress, because it requires more oxidation steps than other devices. Therefore, dislocation-free flash process should be optimized.