• Smart Structures and Systems
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• v.20 no.5
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• pp.595-605
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• 2017

The present article reported the thermal buckling strength of the sandwich shell panel structure and subsequent improvement of the same by embedding shape memory alloy (SMA) fibre via a general higher-order mathematical model in conjunction with finite element method. The geometrical distortion of the panel structure due to the temperature is included using Green-Lagrange strain-displacement relations. In addition, the material nonlinearity of SMA fibre due to the elevated thermal environment also incorporated in the current analysis through the marching technique. The final form of the equilibrium equation is obtained by minimising the total potential energy functional and solved computationally with the help of an original MATLAB code. The convergence and the accuracy of the developed model are demonstrated by solving similar kind of published numerical examples including the necessary input parameter. After the necessary establishment of the newly developed numerical solution, the model is extended further to examine the effect of the different structural parameters (side-to-thickness ratios, curvature ratios, core-to-face thickness ratios, volume fractions of SMA fibre and end conditions) on the buckling strength of the SMA embedded sandwich composite shell panel including the different geometrical configurations.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.1
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• pp.8-18
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• 2008

In this paper, we propose an efficient algorithm using wavelet transform for still image database retrieval. Especially, it uses only the lowest frequency sub-band in multi-level wavelet transform so that a retrieval system uses a smaller quantity of memory and takes a faster processing time. We extract different textured features, statistical information such as mean, variance and histogram, from low frequency sub-band. Then we measure the distances between the query image and the images in a database in terms of these features. To obtain good retrieval performance, we use the first feature (mean and variance of wavelet coefficients) to filter out most of the unlikely images. The rest of the images are considered to be candidate images. Then we apply the second feature (histogram of wavelet coefficient) to rank all the candidate images. To evaluate the algorithm, we create various distorted image databases using MIT VisTex texture images and PICS natural images. Through simulations, we demonstrate that our method can achieve performance satisfactorily in terms of the retrieval accuracy as well as the both memory requirement and computational complexity. Therefore it is expected to provide good retrieval solution for JPEG-2000 using wavelet transform.

• Journal of Information Processing Systems
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• v.18 no.1
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• pp.97-114
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• 2022

Interest is increasing in electrocardiogram (ECG) signal analysis for embedded devices, creating the need to develop an algorithm suitable for a low-power, low-memory embedded device. Linear approximation of the ECG signal facilitates the detection of fiducial points by expressing the signal as a small number of vertices. However, dynamic programming, a global optimization method used for linear approximation, has the disadvantage of high complexity using memoization. In this paper, the calculation area and memory usage are improved using a linear approximated template. The proposed algorithm reduces the calculation area required for dynamic programming through local optimization around the vertices of the template. In addition, it minimizes the storage space required by expressing the time information using the error from the vertices of the template, which is more compact than the time difference between vertices. When the length of the signal is L, the number of vertices is N, and the margin tolerance is M, the spatial complexity improves from O(NL) to O(NM). In our experiment, the linear approximation processing time was 12.45 times faster, from 18.18 ms to 1.46 ms on average, for each beat. The quality distribution of the percentage root mean square difference confirms that the proposed algorithm is a stable approximation.

• The Journal of Korea Robotics Society
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• v.16 no.4
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• pp.327-335
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• 2021

In this paper, we propose an embedded robot system based on "ROS2 on Yocto" that can support various robots. We developed a lightweight OS based on the Yocto Project as a next-generation robot platform targeting cloud robotics. Yocto Project was adopted for portability and scalability in both software and hardware, and ROS2 was adopted and optimized considering a low specification embedded hardware system. We developed SLAM, navigation, path planning, and motion for the proposed robot system validation. For verification of software packages, we applied it to home cleaning robot and indoor delivery robot that were already commercialized by LG Electronics and verified they can do autonomous driving, obstacle recognition, and avoidance driving. Memory usage and network I/O have been improved by applying the binary launch method based on shell and mmap application as opposed to the conventional Python method. Finally, we verified the possibility of mass production and commercialization of the proposed system through performance evaluation from CPU and memory perspective.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.690-693
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• 2002

According to the growth of communication biz, embedded market rapidly developing in domestic and overseas. Embedded system can be used in various way such as wire and wireless communication equipment or information products. There are lots of developing performance applying speech recognition to embedded system, for instance, PDA, PCS, CDMA-2000 or IMT-2000. This study implement minimum memory of speech recognition engine and DB for apply real time embedded system. The implement measure of speech recognition equipment to fit on embedded system is like following. At first, DC element is removed from Input voice and then a compensation of high frequency was achieved by pre-emphasis with coefficients value, 0.97 and constitute division data as same size as 256 sample by lapped shift method. Through by Levinson - Durbin Algorithm, these data can get linear predictive coefficient and again, using Cepstrum - Transformer attain feature vectors. During HMM training, We used Baum-Welch reestimation Algorithm for each words training and can get the recognition result from executed likelihood method on each words. The used speech data is using 40 speech command data and 10 digits extracted form each 15 of male and female speaker spoken menu control command of Embedded system. Since, in many times, ARM CPU is adopted in embedded system, it's peformed porting the speech recognition engine on ARM core evaluation board. And do the recognition test with select set 1 and set 3 parameter that has good recognition rate on commander and no digit after the several tests using by 5 proposal recognition parameter sets. The recognition engine of recognition rate shows 95%, speech commander recognizer shows 96% and digits recognizer shows 94%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of KIISE:Software and Applications
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• v.33 no.6
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• pp.580-587
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• 2006

As PDA, IMT-2000, and e-Book are developed and popular in these days, the number of users who use these products has been increasing. However, available memory size of these machines is still smaller than that of desktop PCs. In these products, TrueType fonts have been increased in demand because the number of users who want to use good quality fonts has increased, and TrueType fonts are of great use in Windows CE products. However, TrueType fonts take a large portion of available device memory, considering the small memory sizes of mobile devices. Therefore, it is required to reduce the size of TrueType fonts. In this paper, two-phase compression techniques are presented for the purpose of reducing the sire of hangul bitmap data embedded in TrueType fonts. In the first step, each character in bitmap is divided into initial consonant, medial vowel, and final consonant, respectively, then the character is recomposed into the composite bitmap. In the second phase, if any two consonants or vowels are determined to be the same, one of them is removed. The TrueType embedded bitmaps in Hangeul Wanseong (pre-composed) and Hangul Johab (pre-combined) are used in compression. By using our compression techniques, the compression rates of embedded bitmap data for TrueType fonts can be reduced around 35% in Wanseong font, and 7% in Johab font. Consequently, the compression rate of total TrueType Wanseong font is about 9.26%.

• Lingua Humanitatis
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• v.1 no.1
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• pp.235-251
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• 2001

According to Chomskyan grammar, humans can generate and understand an unbounded number of grammatical sentences. Against the background of pure and idealized linguistic competence, this linguistic productivity is argued and understood. In actual utterances, however, there are many limitations of productivity but they are said to come from the general constraints on performances such as capacity of short term memory or attention. In this paper I discuss a problem raised against idealized productivity. I argue that linguistic productivity idealizes our linguistic competence too much. By separating idealized competence from the various constraints of performance, Chomskyan theorists can argue for unlimited productivity. However, the absolute distinction between grammar (pure competence) and parser (actual psychological processes) makes little sense when we explain the low acceptability(intelligibility) of center embedded sentences. Usually, the problem of center embedded sentence is explained in terms of memory shortage or other performance constraints. To explain the low acceptability, however, we need to assume specialized memory structure because the low acceptability occurs only with a specific type of syntactic pattern. 1 argue that this special memory structure should not be considered as a general performance constraint. It is a domain specific (specifically linguistic) constraints and an intrinsic part of human language processing. Recent development of Chomskyan grammar, i.e., minimalist approach seems to close the gap between pure competence and this type of specialized constraints. Chomsky's earlier approach of generative grammar focuses on end result of the generative derivation. However, economy principle (of minimalist approach) focuses on actual derivational processes. By having less mathematical or less idealized grammar, we can come closer to the actual computational processes that build syntactic structure of a sentence. In this way, we can have a more concrete picture of our linguistic competence, competence that is not detached from actual computational processes.

• The KIPS Transactions:PartD
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• v.10D no.2
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• pp.187-194
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• 2003

Main Memory storage system can increase the performance of the system by assigning enough slack time to real-time transactions. Due to its high response time of main memory devices, main memory resident data management systems have been used for location management of personal mobile clients to cope with urgent location related operations. In this paper we have developed a multi-threaded main memory storage system as a core component of real-time retrieval system to handle a huge amount of readers and writers of main memory resident data. The storage system is implemented as an embedded component which is working with the help of a disk resident database system. It uses multi-threaded executions and utilizes latches for its concurrency control rather than complex locking method. It only saves most recent data on main memory and data synchronization is done only when disk resident database asks for update transactions. The system controls the number of read threads and update threads to guarantee the minimum requirements of real-time retrievals.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.