• Journal of Institute of Control, Robotics and Systems
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• v.21 no.11
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• pp.989-995
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• 2015

Due to the recent increase of the importance and demand of security services, the importance of a surveillance monitor system that makes an automatic security system possible is increasing. As the market for surveillance monitor systems is growing, price competitiveness is becoming important. As a result of this trend, surveillance monitor systems based on an embedded system are widely used. In this paper, an object detection algorithm based on an embedded system for a surveillance monitor system is introduced. To apply the object detection algorithm to the embedded system, the most important issue is the efficient use of resources, such as memory and processors. Therefore, designing an appropriate algorithm considering the limit of resources is required. The proposed algorithm uses two background models; therefore, the embedded system is designed to have two independent processors. One processor checks the sub-background models for if there are any changes with high update frequency, and another processor makes the main background model, which is used for object detection. In this way, a background model will be made with images that have no objects to detect and improve the object detection performance. The object detection algorithm utilizes one-dimensional histogram distribution, which makes the detection faster. The proposed object detection algorithm works fast and accurately even in a low-priced embedded system.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.4
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• pp.7-14
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• 2003

A number of embedded wavelet image coding methods have been proposed since the introduction of EZW(Embedded Zerotree Wavelet) algorithm. A common characteristic of these methods is that they use fundamental ideas found in the EZW algorithm. Especially, one of these methods is the SPIHT(Set Partitioning in Hierarchy Trees) algorithm, which became very popular since it was able to achieve equal or better performance than EZW without having to use an arithmetic encoder. In this paper We propose a recursive set partitioning in hierarchy trees(RSPIHT) algorithm for embedded image coding and evaluate it's effectiveness experimentally. The proposed RSPIHT algorithm takes the simple and regular form and the worst case time complexity of O(n). From the viewpoint of processing time, the RSPIHT algorithm takes about 16.4% improvement in average than the SPIHT algorithm at T-layer over 4 of experimental images. Also from the viewpoint of coding rate, the RSPIHT algorithm takes similar results at T-layer under 7 but the improved results at other T-layer of experimental images.

• Journal of Korea Multimedia Society
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• v.4 no.1
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• pp.82-90
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• 2001

Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.6
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• pp.377-384
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• 2017

The scope of the matrix application is so broad that it can not be limited. A typical matrix application area in computer science is image processing. Particularly, radar scanning equipment implemented on a small embedded system requires real-time matrix transposition for image processing, and since its memory size is small, a general matrix transposition algorithm can not be applied. In this case, matrix transposition must be done in disk space, such as flash disk, using a limited memory buffer. In this paper, we analyze and improve a recently published flash disk-based matrix transposition algorithm named as asymmetric sub-matrix transposition algorithm. The performance analysis shows that the asymmetric sub-matrix transposition algorithm has lower performance than the conventional sub-matrix transposition algorithm, but the improved asymmetric sub-matrix transposition algorithm is superior to the sub-matrix transposition algorithm in 13 of the 16 experimental data.

• Journal of Korea Multimedia Society
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• v.14 no.1
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• pp.94-102
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• 2011

To alleviate the size and bandwidth requirement in JPEG2000 system, a new Embedded Compression(EC) algorithm with minor image quality drop is proposed. For both random accessibility and low latency, very simple and efficient hadamard transform based compression algorithm is devised. We reduced LL intermediate memory and code-block memory to about half size and achieved significant memory bandwidth reductions(about 52~73%) through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.723-724
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• 2008

In this paper, we explore face recognition technology for embedded system. We develop an algorithm suitable for systems under ubiquitous environment. The basic requirements includes appropriate data format and ratio of feature data to achieve efficiency of algorithm. Our experiment presents a face recognition technique for handheld devices. The essential parts for face recognition based on embedded system includes; integer representation from floating point calculation and optimization for memory management.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.182-184
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• 2005

An embedded system has been applied to many fields including households and industrial sites. The embedded system is implemented fur image tracking in security area. This system supports a fixed IP far the reliable server operation on TCP/IP networks. A real time video image on the is analyzed to detect a certain invader who jumped into the observed area. The digital camera is connected at the USB host port of the target board. The video images from the video camera is continuously analyzed and displayed at the Linux web-server. The moving vector of the invaders on the continuous image frames is calculated and then it sends the calculated pan/tilt movement. That used Block matching algorithm and edge detection algorithm for past speed. And the displacement vector is used at pan/tilt motor control through RS232 serial cable. The experiment result showed tracking performance by the moving part speed of 10 to 150 pixels/sec.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.95-100
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• 2006

I design an Embedded File System in Linux Operating System by applying modified LZSS compressed algorithm. This suggested Compressed File System which is modified file system of the Linux O.S saves the storage space. The compressed file system supports efficient use of storage space. The suggesting file system solves the small space of embedded system. The suggesting file system of this paper gives effect of the large storage space without extending the storage space.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1394-1402
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• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.4
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• pp.219-225
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• 2013

This paper presents a method using Maximum-Likelihood Linear Regression (MLLR) adaptation to improve recognition performance of Limabeam algorithm for speech recognition using microphone array. From our investigation on Limabeam algorithm, we can see that the performance of filtering optimization depends strongly on the supporting optimal state sequence and this sequence is created by using Viterbi algorithm trained with HMM model. So we propose an approach using MLLR adaptation for the recognition of speech uttered in a new environment to obtain better optimal state sequence that support for the filtering parameters' optimal step. Experimental results show that the system embedded with MLLR adaptation presents the word correct recognition rate 2% higher than that of original calibrate Limabeam and also present 7% higher than that of Delay and Sum algorithm. The best recognition accuracy of 89.4% is obtained when we use 4 microphones with 5 utterances for adaptation.