• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.22-30
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• 2011

Recently, the rising demand for intelligent video surveillance system leads to high-performance face recognition systems. The solution for low-resolution images acquired by a long-distance camera is required to overcome the distance limits of the existing face recognition systems. For that reason, this paper proposes a hardware design of an image resolution enhancement algorithm for real-time intelligent video surveillance systems. The algorithm is synthesizing a high-resolution face image from an input low-resolution image, with the help of a large collection of other high-resolution face images, called training set. When we checked the performance of the algorithm at 32bit RISC micro-processor, the entire operation took about 25 sec, which is inappropriate for real-time target applications. Based on the result, we implemented the hardware module and verified it using Xilinx Virtex-4 and ARM9-based embedded processor(S3C2440A). The designed hardware can complete the whole operation within 33 msec, so it can deal with 30 frames per second. We expect that the proposed hardware could be one of the solutions not only for real-time processing at the embedded environment, but also for an easy integration with existing face recognition system.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.463-472
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• 2009

Real-time operating systems must have satisfying various conditions such as effective scheduling policies, minimized interrupt delay, resolved priority inversion problems, and its applications to be completed within desired deadline. The real-time operating systems, therefore, should be designed and developed to be optimal for these requirements. MicroC/OS-II, a kind of Real-time operating systems, uses the basic priority inheritance with a mutex to solve priority inversion problems. For the implementation of mutex, the kernel in an operating system should provide supports for numerous tasks with same priority. However, MicroC/OS-II does not provide this support for the numerous tasks of same priority. To solve this problem, MicroC/OS-II cannot but using priority reservation, which leads to the waste of unnecessary resources. In this study, we have dealt with new design a protocol, so called TPSP(Temporary Priority Swap Protocol), by an effective solution for above-mentioned problem, eventually enabling embedded systems with constrained resources environments to run applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.54-64
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• 2002

Recently System On a Chip(SoC) design based on IP cores has become the trend of If design To prevent the testing problem from becoming the bottleneck of the core-based design, defining of an efficient test architecture and a successful test methodology are mandatory. This paper describes a test architecture and a test control access mechanism for SoC based on IEEE 1149.1 boundary,scan. The proposed SoC test architecture is fully compatible with IEEE P1500 Standard for Embedded Core Test(SECT), and applicable for both TAPed cores and Wrapped cores within a SOC with the same test access mechanism. Controlled by TCK, TMS, TDI, and TDO, the proposed test architecture provides a hierarchical test feature.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10c
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• pp.402-405
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• 2006

멀티프로세서 환경에서 동작하는 임베디드 시스템을 개발하기 위해서는 소프트웨어 모델분만 아니라 하드웨어 플랫폼에 대한 모델이 필요하다. 이는 개발하고자 하는 소프트웨어가 하드웨어 플랫폼에 어떻게 배치되어 실행할 것인가에 대한 고려가 요구되기 때문이다. 특히 MPSoC(Multiprocessor SoC)에서는 소프트웨어를 배치할 하드웨어 플랫폼에 대한 정보가 필요하기 때문에 설계 과정에서 이들에 대한 모델링이 요구된다. 따라서 본 연구에서는 하드웨어 플랫폼 아키덱처를 정의할 수 있는 이클립스 기반의 플러그인을 개발하고, 이를 이용한 PSM 모델링 방안을 제시한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.65-75
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• 2011

As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.649-652
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• 2013

LEON3 is a 32-bit synthesisable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7-stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the development of LEON3 monitoring software.

• KEPCO Journal on Electric Power and Energy
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• v.6 no.4
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• pp.405-411
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• 2020

In this paper, we designed the COS MEMS system for sensing the falling detection and explosive noise of fuse link in COS (Cut Out Switch) installing on the power distribution. This system analyzed the failure characteristics and an instantaneous breakdown of power distribution. Therefore, our system strengths the industrial competence and guaranties the stable power supply. In this paper, we applied BLE (Bluetooth Low Energy) technology which is suitable protocol for low data rate, low power consumption and low-cost sensor applications. We experimented with LSM6DSOX which is system-in-module featuring 3 axis digital accelerometer and gyroscope boosting in high-performance mode and enabling always-on low-power features for an optimal motion for the COS fuse holder. Also, we used the MP34DT05-A for gathering an ultra-compact, low power, omnidirectional, digital MEMS microphone built with a capacitive sensing element and an IC interface. The proposed COS MEMS system is developed based on nRF52 SoC (System on Chip), and contained a 3-axis digital accelerometer, a digital microphone, and a SD card. In this paper of experiment steps, we analyzed the performance of COS MEMS system with gathering the accelerometer raw data and the PDM (Pulse Data Modulation) data of MEMS microphone for broadcasting the failure of COS status.