• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.10
• /
• pp.1858-1865
• /
• 2007

In this paper, we introduce the design and implementation of satellite IP modem. The designed satellite IP modem shows the performance of 0.2% overhead, BER=10-5 when Eb/No=6dB, frequency offset of 8KHz, data rate up to 1536Kbps, $F_{if}=140MHz$. The designed system is verified through software simulation and then implemented with MPC86x communication processor, TMS320C6416 DSP, and Altera FPGA. Since each hardware unit is implemented in daughter board for modularity, we can reduce the development time and easily improve the performance with using better processor. Linux is used for embedded OS because it shows better performance in IP manipulation multitask processing, and hardware control through device driver. The implemented system is tested and verified with channel simulator. Since the proposed IP modem shows small size and light weight, that can be used anywhere with easy if you need IP environment.

• Journal of Aerospace System Engineering
• /
• v.13 no.3
• /
• pp.15-22
• /
• 2019

In this paper, a global and local flight path system for autonomous flight of the UAV is proposed. The overall system is based on the ROS robot operating system. The UAV in-built computer detects obstacles through 2-D Lidar and generates real-time local path and global path based on VFH and Modified $RRT^*$-Smart, respectively. Additionally, a movement command is issued based on the generated path on the UAV flight controller. The ground station computer receives the obstacle information and generates a 2-D SLAM map, transmits the destination point to the embedded computer, and manages the state of the UAV. The autonomous UAV flight system of the is verified through a simulator and actual flight.

• International Journal of Computer Science & Network Security
• /
• v.23 no.1
• /
• pp.153-163
• /
• 2023

This study is situated in the context of intelligent transport systems, where in-vehicle devices assist drivers to avoid accidents and therefore improve road safety. The vehicles present in a given area form an ad' hoc network of vehicles called vehicular ad' hoc network. In this type of network, the nodes are mobile vehicles and the messages exchanged are messages to warn about obstacles that may hinder the correct driving. Node mobilities make it impossible for inter-node communication to be end-to-end. Recognizing this characteristic has led to delay-tolerant vehicular networks. Embedded devices have small buffers (memory) to hold messages that a node needs to transmit when no other node is within its visibility range for transmission. The performance of a vehicular delay-tolerant network is closely tied to the successful management of the nodes' transit buffer. In this paper, we propose a message transit buffer management model for nodes in vehicular delay tolerant networks. This model consists in setting up, on the one hand, a policy of dropping messages from the buffer when the buffer is full and must receive a new message. This drop policy is based on the concept of intermediate node to destination, queues and priority class of service. It is also based on the properties of the message (size, weight, number of hops, number of replications, remaining time-to-live, etc.). On the other hand, the model defines the policy for selecting the message to be transmitted. The proposed model was evaluated with the ONE opportunistic network simulator based on a 4000m x 4000m area of downtown Bouaké in Côte d'Ivoire. The map data were imported using the Open Street Map tool. The results obtained show that our model improves the delivery ratio of security alert messages, reduces their delivery delay and network overload compared to the existing model. This improvement in communication within a network of vehicles can contribute to the improvement of road safety.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1993.06a
• /
• pp.975-976
• /
• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.4
• /
• pp.2217-2224
• /
• 2014

This paper deals with system development which measures 12 channel ECG using medical analog front end(AFE) and discriminates arrythmia through signal analysis. Recently, occurrences of cardiac arrest have been increased. So the need of system that diagnoses an arrythmia which results in cardiac arrest is increasing. There are some drawbacks of conventional 12 channel ECG system that it occupies bulk and consists of complicated circuit. To improve those, we made up the system composed of medical AFE, algorithm for discriminating arrythmia and DSP for signal processing. This system can be monitored 12 channel ECG waveforms and the discriminant analysis result of arrhythmia through 7" LCD and received the input through touch pannel. In this study, we conducted normal operation test about output signal of ECG simulator(normal/abnormal ECG signal) to verify the implemented system and performance evaluation of the optimization process for applying arrhythmia algorithm to an embedded environment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.11a
• /
• pp.55-55
• /
• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• The Journal of Korean Academy of Prosthodontics
• /
• v.41 no.2
• /
• pp.232-242
• /
• 2003

Statement of problem : Fiber-reinforced posts have lower modulus of elasticity than titanium post or cast post-core. With this similar elasticity to that of dentin, fiber-reinforced posts have been known to have a tendency to reduce the risk of root fracture. However, there were few studies on the teeth restored with fiber-reinforced posts under the condition of reduced periodontal support. Purpose : The purpose of this study was to evaluate the fracture strength and failure mode of endodontically treated teeth restored with fiber-reinforced posts and titanium posts under the condition of reduced periodontal support. Material and method : Extracted human maxillary incisor roots were divided into 3 groups (group 1 carbon fiber post, group 2 : glass fiber post, and group 3 : titanium alloy post). After coronectomy and endodontic treatment, teeth were restored with each post systems and resin core according to the manufacturer's recommendation. Then, teeth with simulated periodontal ligament were embedded in the acrylic resin blocks at the level of 4 mm below the cemento-enamel junction. Each specimen was exposed to $10^5$ load cycles with average 30 N force in $36.5^{\circ}C$ water using a computer-controlled chewing simulator. Loads were applied at $45^{\circ}$ angle to the long axis of the teeth. After cyclic loading, teeth were subjected a compressive load until failure at a crosshead speed of 0.5 mm/min. Fracture strength (N) and failure mode were examined. The fracture strength was analyzed with one-way ANOVA and the Scheffe adjustment at the 95% significance level. Results and conclusion : The results were as follows. 1. There was no statistically significant difference in the mean fracture strength among the groups (P<.05). 2. Carbon fiber post and glass fiber post group showed less root fracture tendency than control group. 3. All specimens with root fractures showed fracture lines above the level of acrylic resin block, except for only one specimen in group 3.