• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.1
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• pp.219-224
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• 2017

Recently, the importance of DRAM is very significant not only in embedded systems and mobile devices but also in high-end modern microprocessors and multicore processors. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the microprocessor performance. In this paper, a microprocessor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the microprocessor performance has been evaluated.

• Journal of Forest and Environmental Science
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• v.24 no.3
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• pp.143-149
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• 2008

We conduct economic analysis of the snow damage on sugi (Cryptomeria japonica) forest stands in Toyama Prefecture, Japan. We utilize a single tree and distant independent growth simulator called "Silv-Forest." With this growth simulator, we developed an optimization model by dynamic programming, called DP-Silv (Dynamic Programming Silv-Forest). The MS-PATH (multiple stage projection alternative technique) algorithm was embedded as a searching algorithm of dynamic programming. The height / DBH ratio was used to constrain the thinning regime for snow damage protection. The optimal rotation age turned out to be 65 years for the non-restricted case, while it was 50 years for the restricted case. The difference in NPV of these two cases as the induced costs ranged from 179,867 to 1,910,713yen/ha over the rotation age of 20 to 75 years. Under the optimal rotation of 65 years, the cost became 914,226 yen/ha. The estimated annual payment based on the difference in NPV, was from 9,869 yen/ha/yr to 85,900 yen/ha/yr. All in all, 10,000 yen/ha/yr to 20,000 yen/ha/yr seems to cover the payment from the rotation age of 35 to 75 years.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1460-1471
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• 2007

A 3-Dimensional engine in a mobile embedded device is divided into a C-based OpenGL/ES and a Java-based JSR184 which interprets and executes a byte code in a real-time. In these two standards, the JSR184 supporting Java objects uses more processor resources than an OpenGL/ES and thus has a constraint when it is used in an embedded device with a limited computing power. On the other hand, 3-Dimensional contents employed in existing personal computer are created by utilizing advantages of Java and secured numerous users in European market, due to the good quality in contents and extensive service in a commercial network, GSM. Because of the reason, a mobile embedded device used in a GSM network needs a JSR184 which can provide an existing Java-based 3-Dimensional contents without extra conversion processes, but the current version of Java-based 3-Dimensional engine has drawbacks in application to commercial products because it requires more computing power than the mobile embedded device. This paper proposes a binding technique with the advantages of Java objects to improve a processing speed of 3-Dimensional contents in limited resources of a mobile embedded device. The technique supports a JSR184 standard interface in the upper layer to utilize 3-Dimensional contents using Java, employs a different code-conversion language, KNI(Kilo Native Interface), in the middle layer to interface between OpenGL/ES and JSR184, and embodies an OpenGL/ES standard in the lower layer. The validity of the binding technique is demonstrated through a simulator and a FPGA embedding an ARM.

• ETRI Journal
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• v.30 no.1
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• pp.47-58
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• 2008

In sensor networks, analyzing power consumption before actual deployment is crucial for maximizing service lifetime. This paper proposes an instruction-level power estimator (IPEN) for sensor networks. IPEN is an accurate and fine grain power estimation tool, using an instruction-level simulator. It is independent of the operating system, so many different kinds of sensor node software can be simulated for estimation. We have developed the power model of a Micaz-compatible mote. The power consumption of the ATmega128L microcontroller is modeled with the base energy cost and the instruction overheads. The CC2420 communication component and other peripherals are modeled according to their operation states. The energy consumption estimation module profiles peripheral accesses and function calls while an application is running. IPEN has shown excellent power estimation accuracy, with less than 5% estimation error compared to real sensor network implementation. With IPEN's high precision instruction-level energy prediction, users can accurately estimate a sensor network's energy consumption and achieve fine-grained optimization of their software.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.54 no.3
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• pp.141-147
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• 2005

In this paper, We are going to propose the fire protection system with using CAN(Controller Area Network). The larger, higher and deeper buildings are, the more dangerous people are when fire happens. We should be aware of the problems of prior fire protection system. Therefore, we construct embedded system based on CAN communication that is capable of N:N communication, and build independent fire protection system. If the fire is occurred on the building, the problem is that how fast we can detect the fire and put off it by using available system. this is major factor that reduces damage of our wealth. therefore in this studies We would like to design more stable system than current system. this system that is based on CAN communication which is available N:N communication constructs and is designed to compensate for each fault so that our aim is to reduce the line of system and cost of installation and to suppose future type fire protection system. We are simulated by NIST FDS(Fire Dynamics Simulator) to prove the efficiency of this system.

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.621-626
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• 2005

Recently, flash memory is widely used in various embedded applications since it has many advantages in terms of non-volatility, fast access speed, shock resistance, and low power consumption. However, it requires a software layer called FTL(Flash Translation Layer) due to its hardware characteristics. We present a new FTL algorithm named LSTAFF(Large State Transition Applied Fast flash Translation Layer) which is designed for large block flash memory The presented LSTAFF is adjusted to flash memory with pages which are larger than operating system data sector sizes and we provide performance results based on our implementation of LSTAFF and previous FTL algorithms using a flash simulator.

• Journal of IKEEE
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• v.17 no.4
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• pp.484-491
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• 2013

In this paper, we proposed an internal multiband loop embedded monopole antenna for mobile handset that could be used for smart phones. The proposed antenna has a volume of 40 mm(W) ${\times}$ 15 mm(L) ${\times}$ 5 mm(H), ground plane size is 40 mm(W) ${\times}$ 80 mm(L), and covers the GSM900 (Global System for Mobile communications : 880-960 MHz), K-PCS (Korea-Personal Communications Service : 1750-1870 MHz), US-PCS (US Personal Communications Service : 1850-1990 MHz), WCDMA (Wideband Code Division Multiple Access : 1920-2170 MHz), Wibro (2300-2390 MHz), Bluetooth (2400-2483 MHz) and WLAN (Wireless Local Area Network : 2400-2483.5 MHz) bands for VSWR (voltage standing wave ration) less than 3. The proposed loop adding design at middle section of longest branch showed wide impedance bandwidth for the lowest resonance frequency band. The proposed antenna have a lowest resonance frequency band from 738 MHz to 1075 MHz for S11 value of -6dB. A HFSS (High Frequency Structure Simulator) of the Ansys Corporation based on a finite element method is employed to analyze the proposed antenna in the design process and to compare the simulation and experimental results.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.129-132
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• 2002

AE64000 is the 64-bit high-performance microprocessor that ADC Co. Ltd. is developing for an embedded environment. It has a 5-stage pipeline and uses Havard architecture with a separated instruction and data caches. It also provides SIMD-like DSP and FP operation by enabling the 8/16/32/64-bit MAC operation on 64-bit registers. AE64000 processor implements the EISC ISA and uses the instruction folding mechanism (Instruction Folding Unit) that effectively deals with LERI instruction in EISC ISA. But this unit makes branch prediction behavior difficult. In this paper, we designs a branch predictor optimized for AE64000 Pipeline and develops a AES4000 simulator that has cycle-level precision to validate the performance of the designed branch predictor. We makes TAC(Target address cache) and BPT(branch prediction table) seperated for effective branch prediction and uses the BPT(removed indexed) that has no address tags.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.735-745
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• 2001

Processors require both intensive and extensive functional verification in their design phase due to their general purpose. The proposed random vector verification method for embedded control RISC cores meets this goal by contributing assistance for conventional methods. The proposed method proved its effectiveness during the design of CalmRISCTM-32 developed by Yonsei Univ. and Samsung. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors if any difference is found between them. Consequently, it successfully covers errors designers easily pass over and establishes other new error check points.

• Journal of the Korean Solar Energy Society
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• v.31 no.2
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• pp.16-21
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• 2011

Since the maximum power operating point(MPOP) of PCS alters with changing atmospheric conditions temperature conditions shadow conditions it is important to operate for PCS to keep maximum power point tracking(MPPT) continuously. This paper presents the results of modeling PV system by PSIM simulator and investigates the influence on the PV system from aspect of power quality i.e. voltage drop. This paper investigates four MPPT algorithms; Perturbation & Observation(P&O) Improved P&O Incremental Conductance(Incond) Differential coefficient method simulated with irradiation temperature change and shadow conditions.