• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.500-502
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• 2003

In this paper, we have designed a platform with MSC8101 processor for networked converter monitoring and diagnosis. MSC8101 is a dual processor type SOC(System On a Chip), which is consist of 16bit DSP and 32bit RISK CPM. As it have DSP and CPM, MSC8101 is competent for networking and data processing application. This MSC8101 platform is designed for networked monitoring and diagnosis, so it is important processing ability and networking capability.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.43-45
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• 2011

Very Long Instruction Word (VLIW) executes multiple instructions in parallel. In order to exploit higher performance, i.e., higher parallelism, VLIW compiler groups as many instructions into one word as possible. In this paper, we show how to construct a VLIW C compiler based on GCC for CDSP32 (Compact Digital Signal Processor 32-bit) which is an embedded DSP processor to issue two instructions in one VLIW. Also, we evaluated the compiler on EEMBC benchmark; the experiment result showed that the total number of dynamic instructions of the VLIW compiler was reduced by 18% on average over without VLIW instruction scheduling.

• The KIPS Transactions:PartA
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• v.12A no.4 s.94
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• pp.305-312
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• 2005

In this paper, we present algorithm-level techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform(FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations on high-level and through low-level simulation. For FFT, our designs dissipated an average of $50\%$ less energy than the design from the Xilinx library and $56\%$ less than the DSP. Our designs showed an EAT factor of 10 times improvement over the embedded processor. These results provide a concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that PFGAs can achieve this performance while still dissipating less energy than the other two types of devices.

• The Journal of the Acoustical Society of Korea
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• v.30 no.3
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• pp.115-122
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• 2011

In this paper, we present a method to estimate an accurate real-time sound source direction based on time delay of arrival by using generalized cross correlation with four cross-type microphones. In general, existing systems have two disadvantages such as system embedding limitation due to the necessity of data acquisition for signal processing from microphone input, and real-time processing difficulty because of the increased number of channels for sound direction estimation using DSP processors. To cope with these disadvantages, the system considered in this paper proposes hardware design for enhanced real-time processing using microphone array signal processing. An accurate direction estimation and its design time reduction is achieved by means of an efficient hardware design using spatial segmentation methods and verification techniques. Finally we develop a system which can be used for embedded systems using a sound codec and an FPGA chip. According to experimental results, the system gives much faster real-time processing time compared with either PC-based systems or the case with DSP processors.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.41-52
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• 2011

It is important to reduce computational complexity of de-blocking filter for real-time implementation, because it accounts for a great part of total computational complexity of the decoder. Because there are a lot of conditional branches and memory accesses in a decoding loop, it is not easy to speed up the de-blocking filter. Therefore, this paper presents a new algorithm of de-blocking filter minimizing conditional branches and memory accesses. The proposed structure of de-blocking filter enables filter operation to parallelize by software pipelining. The proposed optimization method was implemented on a TMS320DM6467 EVM board and we achieved approximately 46% cycle reduction, compared with that of FFmpeg.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.5
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• pp.80-86
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• 2005

Induction motors are a critical component of many industrial processes and are frequently integrated in commercially available equipment. Safety, reliability, efficiency, and performance are some of the major concerns of induction motor applications. Fault tolerant control (FTC) strives to make the system stable and retain acceptable performance under the system faults. All present FTC method can be classified into two groups. The first group is based on fault detection and diagnostics (FDD). The second group is includes of FDD and includes methods such as integrity control, reliable stabilization and simultaneous stabilization. This paper presents the fundamental FDD-based FTC methods, which are capable of on-line detection and diagnose of the induction motors. Therefore, our group has developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. This paper presents its architecture. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module processes the stator current, voltage, temperatures, vibration signal of the motor.

• Journal of Satellite, Information and Communications
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• v.8 no.4
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• pp.26-29
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• 2013

In order to estimate people crowdedness in public area, the texture based method or motion based method can be used. In this paper we have proposed a mixed method. By designating the region of interest, we made the degree of crowdedness more accurate. The feature normalization also reduced the image distortion which results from difference of camera angle. The proposed system was optimized to real time embedded hardware system.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.2
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• pp.201-206
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• 2004

This study attempted to develop a speech recognition module applied to a wheelchair for the physically handicapped. In the proposed speech recognition module, TMS320C32 was used as a main processor and Mel-Cepstrum 12 Order was applied to the pro-processor step to increase the recognition rate in a noisy environment. DTW (Dynamic Time Warping) was used and proven to be excellent output for the speaker-dependent recognition part. In order to utilize this algorithm more effectively, the reference data was compressed to 1/12 using vector quantization so as to decrease memory. In this paper, the necessary diverse technology (End-point detection, DMA processing, etc.) was managed so as to utilize the speech recognition system in real time

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.143-150
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• 2012

In this paper, we introduce an intelligent quadruped walking robot that can perform stable walking and a couple of intelligent behaviors. The developed robot has two sets of ultrasonic sensors and six sets of infrared sensors and can perform obstacle avoidance by detecting obstacles and estimating the distances and directions of those obstacles. The robot also has a stereo camera and can paly soccer by detecting a ball and estimating the 3 dimensional coordinates of the ball. In performing those intelligent behaviors, the robot needs to have the capability of generating its walking patterns, solving the inverse kinematics problem, and interfacing several sensors in realtime. Therefore we designed a hierarchical controller that consists of a main controller and an auxiliary controller. The main controller is a 32-bit DSP that can perform fast floating-point opertaion and the auxiliary one is a 8-bit micro-controller. We showed that the developed quadruped walking robot successfully perform those intelligent behaviors through experiments.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1954-1955
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• 2007

This paper presents a modeling method of speed controller for DC motor drive system by using the Embedded Target for TI C2000 DSP in MATLAB/SIMULINK. Speed controller is easily designed and implemented by using the MATLAB/SIMULINK program, and speed control response and stability of the DC motor can be improved. Feedback of motor speed is processed through C28x QEP(Quadrature Encoder Pulse) from encoder pulse. The controller is designed as PI speed controller. Simulation program is drawn using SIMULINK. Then a real-time program for speed control of the DC motor is downloaded into the eZdsp F2811 control board. Speed control response is verified through simulations and experiments.