• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2217-2224
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• 2014

This paper deals with system development which measures 12 channel ECG using medical analog front end(AFE) and discriminates arrythmia through signal analysis. Recently, occurrences of cardiac arrest have been increased. So the need of system that diagnoses an arrythmia which results in cardiac arrest is increasing. There are some drawbacks of conventional 12 channel ECG system that it occupies bulk and consists of complicated circuit. To improve those, we made up the system composed of medical AFE, algorithm for discriminating arrythmia and DSP for signal processing. This system can be monitored 12 channel ECG waveforms and the discriminant analysis result of arrhythmia through 7" LCD and received the input through touch pannel. In this study, we conducted normal operation test about output signal of ECG simulator(normal/abnormal ECG signal) to verify the implemented system and performance evaluation of the optimization process for applying arrhythmia algorithm to an embedded environment.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.411-418
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• 2009

Vector quantization algorithm based on fuzzy clustering has been widely used in the field of data compression since the use of fuzzy clustering analysis in the early stages of a vector quantization process can make this process less sensitive to its initialization. However, the process of fuzzy clustering is computationally very intensive because of its complex framework for the quantitative formulation of the uncertainty involved in the training vector space. To overcome the computational burden of the process, this paper introduces an array architecture for the implementation of fuzzy vector quantization (FVQ). The arrayarchitecture, which consists of 4,096 processing elements (PEs), provides a computationally efficient solution by employing an effective vector assignment strategy during the clustering process. Experimental results indicatethat the proposed parallel implementation providessignificantly greater performance and efficiency than appropriately scaled alternative array systems. In addition, the proposed parallel implementation provides 1000x greater performance and 100x higher energy efficiency than other implementations using today's ARMand TI DSP processors in the same 130nm technology. These results demonstrate that the proposed parallel implementation shows the potential for improved performance and energy efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.182-192
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• 1999

The advance of the MPEG(Moving Picture Expert Group) and DSP(Digital Signal Processing) technologies lead the energence of the information appliances which are gradually digitalized and embedded the high-speed networking function. This paper proposes a CHANCE(Cost-effective Home ATM Network for the Consumer Electronics) protocol supporting the ATM-based high-speed networking between the information appliances within the home, and designs its specific functions including the network management and signalling function. The CHANCE protocol is basically based on the tree topology, and supports the plug-and-play function by using only the header field of the ATM cells. Unlike the existing ATM Warren protocol which uses the source routed addressing scheme to control the in-home devices from the Warren controller, the CHANCE protocol can support the inter-device controls as well as the controls from the CHANCE controller by using the switch and device identifier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1C
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• pp.28-36
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• 2011

As Power Line has been already installed over 60% of a residential area all over the world, Broadband Service has been possible using high-speed PLC(Power Line Communication) without new access line installed for Internet access. Because of such reason, PLC is researched as the most suitable service for Last Mile Solution. But, Power Line is designed for transmitting electric power, so peripheral Wireless Communication System is affected by a leak of electric wave. In this paper, we propose a High Performance Notch Filter algorithm in comparison with a existing notch filter for reduction of interference between existing Wireless Communication Service and Power Line Service. In addition, we implement the Notch Filter emulator appling a High Performance Notch Filter and using a embedded board.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.30-37
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• 2007

Hardware for monitoring the water quality is developed using water fleas. Water flea is a frequently used biological sensor for monitoring the water quality. Water fleas quickly respond to the incoming toxic water by changing their activity when they are exposed. By measuring the activity of water fleas, the incoming toxic water is instantly detected in real time. So far the measurement of activity of water fleas has been done with a system equipped with a light source of LED and a light detector of photo transistor. Water flea itself is, however, sensitive to light resulting in incorrect response and the system has two inconvenient separate parts of the light source and the detector. This paper suggests a system using a CCD camera instead of a light source and a detector. The suggested system processes the image data from the CCD camera in real time without any delay. The developed system becomes a part of the remote water monitoring embedded system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.66-74
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• 2008

Surveillance system using active tracking camera has no distance limitation of surveillance range compared to supersonic or sound sensors. However, complex motion tracking algorithm requires huge amount of computation. Compared to conventional methods using DSPs or embedded processors, this paper proposes and implements a novel motion tracker unit that detects and extracts motion information of moving objects by using picture difference of consecutive frames. The proposed motion tracker unit was implemented in FPGA with about 13,000 gates. It processes NTSC format video and was verified by embedding it into the active surveillance camera system. We also propose and implements a motion estimator unit linkable to video codec by embedding the proposed motion tracker unit into ready-made motion estimator unit. The implemented motion estimator unit is about 17,000 gates in $0.35{\mu}m$ process.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.8
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• pp.748-756
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• 2015

In this paper, we developed a miniaturized real time video compression system satisfying the military environment using ADV212 and FPGA. We present an efficient hardware design scheme for the weight reduction of the device and also a software solution to deal with noisy image signals. Experimental results show that the frame delay is reduced by a factor of 2 or 3 and the device's weight is decreased by a factor of 6 to 7. In order to prove the reliability for the military usage of this development, we examine the environmental test (MIL-STD-810G) and EMI test (MIL-STD-461F). Experimental results show that the developed system satisfies the requirements.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.148-149
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• 2007

We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.