• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.17-24
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• 2014

In this paper, we implement and evaluate the performance of a vector-based rasterization algorithm for 3D graphics by using a SIMD (single instruction multiple data) many-core processor architecture. In addition, we evaluate the impact of a data-per-processing elements (DPE) ratio that is defined as the amount of data directly mapped to each processing element (PE) within many-core in terms of performance, energy efficiency, and area efficiency. For the experiment, we utilize seven different PE configurations by varying the DPE ratio (or the number PEs), which are implemented in the same 130 nm CMOS technology with a 500 MHz clock frequency. Experimental results indicate that the optimal PE configuration is achieved as the DPE ratio is in the range from 16,384 to 256 (or the number of PEs is in the range from 16 and 1,024), which meets the requirements of mobile devices in terms of the optimal performance and efficiency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.307-311
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• 2015

In this paper, we propose an efficient fault-recovery technique for CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture. The proposed technique is intra/inter-CGRA co-reconfiguration technique based on a ring-based sharing fabric (RSF) and it enables exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. Experimental results show that the proposed approaches achieve up to 73% fault recoverability when compared with completely connected fabric (CCF).

• The Journal of Korean Academic Society of Nursing Education
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• v.23 no.2
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• pp.135-145
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• 2017

Purpose: The purpose of this study was to develop a program outcomes assessment system based on Course Embedded Assessment for nursing education. Methods: This study was conducted in accordance with the procedures of the developmental research method. Results: The major results are as follows. 1) The program outcomes were measured according to the Analytic Hierarchy Process. 2) The Course Embedded Assessment matrix was made according to program outcomes' weight, the curriculum-organizing principle, and achievement levels. 3) The Course Embedded Assessment rubric was developed in logical process, and consisted of a performance criterion, and rating scale. The content validity index of the Course Embedded Assessment rubric was 0.85. 4) An evaluation guideline and 12 documents were developed to facilitate the performance of the assessment system. 5) The average content validity index of the Course Embedded Assessment-based program outcomes assessment system was as high as 0.89. Conclusion: A Course Embedded Assessment-based program outcomes assessment system is more suitable for accreditation of nursing education than previous studies. Because this system evaluates the process of achievement as well as program outcomes, the results can also serve as immediate feedback to improve the educational process. Above all, this system facilitates that students check their achievements and strive to acquire core competencies in nursing.

• Annual Conference of KIPS
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• 2015.10a
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• pp.208-210
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• 2015

임베디드 시스템에서 멀티코어 프로세스의 채택이 늘어나고 있다. 멀티코어 시스템이 태스크들을 효율적으로 병렬화하여 성능을 극대화하였는지 살펴보기 위해서는 태스크들의 스케줄링 결과를 분석하고 시각화 해주는 도구가 필요하다. 본 논문에서는 멀티코어 임베디드 시스템을 위한 태스크 스케줄링 결과 시각화 도구를 소개한다. 자원 제약이 있는 임베디드 타켓 디바이스의 부하를 줄이기 위해 스케줄링 결과는 호스트 컴퓨터에 전달되어 분석 및 시각화된다. 시각화 형태는 시스템의 전체 동작을 한 눈에 파악할 수 있게 해주는 그래프 형태와 정밀한 분석을 가능하게 해 주는 리스트 형태로 제공된다. 제시된 도구는 멀티코어 임베디드 시스템의 태스크들의 스케줄링 결과를 쉽고 정확하게 파악할 수 있게 해 주어 시스템의 성능 향상에 도움을 준다.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.67-73
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• 2020

In this paper, we used FEM technique to perform warpage and von Mises stress analysis on PCB according to the cavity structures of embedded PCB for FCCSP and the types of prepreg material. One-half substrate model and static analysis are applied to the FEM. According to the analysis results of the warpage, as the gap between the cavity and the chip increased, warpage increased and warpage increased when prepreg material with higher modularity and thermal expansion coefficient was applied. The analysis results of the von Mises stress show that the effect of the gap between the cavity and the chip varies depending on prepreg material. In other words, when material whose coefficient of thermal expansion is significantly higher than that of core material, the stress increased as the gap between the cavity and the chip increased. When the prepreg with the coefficient of thermal expansion lower than the core material is applied, the result of stress is opposite. These results indicate that from a reliability perspective, there is a correlation between the structure of the cavity where embedded chips are loaded and prepreg material.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.13-18
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• 2000

Low temperature co-fired ceramics on metal (LTCC-M) is efficient for embedding passive components with good tolerance in a module due to the dimensional stability in x and y directions by the constraint of metal core during the firing. In addition, the radiation noise can be reduced by metal core. In this paper, embedded passive components were introduced and a power amplifier module (PAM) fabricated by using the passive components was explained. The embedded passive components in test patters showed the tolerance of 10~20% and the good repeatability in tolerance of embedded passives was maintained in module fabrication. The shortened traces in multi chip modules (MCMs) make the signal delay time decreased and the embedded passives simplify the packaging processes owing to the less solder points, which enhance the electrical performance and increase the reliability of the modules. The LTCC-M technology is one of the promising candidates for RF application and is expected to expand its applications to power and high performance devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.284-299
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• 2014

Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.

• IE interfaces
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• v.23 no.1
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• pp.35-47
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• 2010

This paper presents a structured framework for developing the embedded subsystem, called ESDMP (Embedded Subsystem Development Methodology for POP), which is one of core components at the development of POP (Point Of Production) system. It is essential that embedded subsystem development methodology must be closely related to the general information system development methodology from the early stage of system development. Therefore, this paper investigates the PDSM (Production System Development Methodology) that is developed by Korea Technology and Information Promotion Agency for SMEs and widely utilized at the fields of POP system development, and proposes the embedded subsystem development methodology aligned with each step of PSDM. The main characteristics of proposed methodology are as follows : First, it is developed to link each step of embedded subsystem development with relating steps of PSDM from the early stage of feasibility study. Second, it provides the procedure for designing and implementing hardware and software simultaneously. Third, it includes the method of reusability for developed products and modules.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.1
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• pp.59-65
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• 2022

Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.539-548
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• 2015

In this paper, shared memory feature was developed in multi-core system with different OS for different processor-specific bus, while conducting an experiment on shared memory feature between the two processors based on embedded Linux system. For the purpose of developing shared memory in dual bus structure, memory controller was used, while managing shared memory segment through list data structure. For AMP multi-core test, Linux OS was installed in 2 processor cores. In addition, it verified the creation and use of shared memory by using kernel module implemented to test shared memory.