• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.19-39
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• 2003

Embedded Laminate Embedded RF Functional Blocks.Base Library of Laminate Embedded Filters and Baluns developed for 2.4GHz Applications -S-Parameters are provided at connection points -Utilizes a low cost 2 core construction.Statistical Variation Study in Report Phase.Measurements over variants show solid performance.Filters and Baluns are available for customer use.Laminate Embedded RF Functions - Various Filters, BALUNs, couplers, etc. for Bluetooth, 802.11, and Cellular.LTCC Embedded RF Functions - Various Filters, BALLNs, Diplexers, Antenna Switches, couplers, etc. for Bluetooth, 802.11, and Cellular.Eulbedded Passives - Various Inductor topologies Performance different than ideal or discrete inductor Must look at inductor performance in overall RF function - Working on embedded ceramic capacitors in laminate . Embedded Shields - Program in place to identify and define key design rules

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.1
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• pp.18-24
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• 2003

A three node triangular element with drilling rotations incorporating improved higher-order zig-zag theory(HZZT) is developed to analyze the vibration of pretwisted composite plates with embedded damping layer. Shear force matching conditions are enforced along the interfaces between the embedded damping patch and the border patch by matching the shear forces of the embedded damping patch to the shear forces of the adjacent border patch. The natural frequencies and modal loss factors are calculated for cantilevered pretwisted composite blade with damping core with the present triangular element, and compared to experiments and MSC/NASTRAN using a layered combination of plate and solid elements.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• The Journal of the Acoustical Society of Korea
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• v.25 no.2E
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• pp.85-88
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• 2006

Blade-vortex interaction (BVI) is one of the most important phenomena in rotor flow since it causes undesirable intense vibration and noise. Since three dimensional Euler or Navier-Stokes solutions to BVI require very high computational cost, BVI has been approximated by airfoil-vortex interaction (AVI) in chordwise planes. To describe more realistic situations with AVI, three dimensional vortex informations such as position, core size and strength are embedded artificially to Computational Aeroacoustics (CAA) calculation at each computational time step. To implement this requirement, in this paper, a technique called free vortex embedded method was used. And the solution by this method was compared with the solution by conventional method for interaction between freely convected vortex and airfoil. For the application to three dimensional free vortex embedded CAA, two dimensional free vortex embedded CAA method was validated in advance.

• International Journal of Internet, Broadcasting and Communication
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• v.9 no.3
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• pp.9-16
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• 2017

Recently, more users have been using IoT embedded systems. Since the wireless network function is a basic and core function in most embedded systems, new security threats and weaknesses are expected to occur. In order to resolve these threats, it is necessary to investigate the security issues in the development stages according to the Security Development Lifecycle (SDL). This study analyzes the vulnerabilities of the embedded systems equipped with the wireless network function, and derives possible security threats and how dangerous such threats are. We present security risks including bypassing the authentication stage required for accessing to the embedded system.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.653-656
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• 2003

We have designed embedded web sewer system and ported Linux operating system version 2.4.5 at our system. And then We implemented to control and monitor widely separated hardware and implemented to monitor widely separated image using CMOS image sensor HV7131B. Web server is the Boa web server with General Public License. We designed for this system using of Intel's SA1110 ARM core base processor and connecting input and output device at GPIO port of SA1110. Device driver of General purpose I/O for Embedded Linux OS is designed. And then the application program controlling driver is implemented to use of common gate interface C language. User is available to control and monitor at client PC. This method have benefit to reduce the Expenditure of hardware design and development time against PC base system and have various and capacious application against firmware base system.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.17-22
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• 2009

DaVinci processors are popular media processors for implementing embedded multimedia applications. They support dual core architecture: ARM9 core for video I/O handling as well as system management and peripheral handling, and DSP C64+ core for effective digital signal processing. In this paper, we propose our efforts for optimal implementation of object tracking algorithm in DaVinci-based smart camera which is being designed and implemented by our laboratory. The smart camera in this paper is supposed to support object detection, object tracking, object classification and detection of intrusion into surveillance regions and sending the detection event to remote clients using IP protocol. Object tracking algorithm is computationally expensive since it needs to process several procedures such as foreground mask extraction, foreground mask correction, connected component labeling, blob region calculation, object prediction, and etc. which require large amount of computation times. Thus, if it is not implemented optimally in Davinci-based processors, one cannot expect real-time performance of the smart camera.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.