• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.1
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• pp.241-249
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• 2017

Recently, as a vehicle black box device has propagated, it has been increasingly used as a legal proof and there are the needs to verify an integrity of the video data. However, since the black box classified as the embedded system has a small capacity and low processing speed, there are limitations to the storage of video files and the integrity verification processing. In this paper, we propose a novel method for video files integrity in the black box environment with limited resources by using lightweight hash function LSH and the security of HMAC. We also present the test results of CPU idle rate at integrity verification in vehicle black box device by implementing this method, and verify the effectiveness and practicality of the proposed method.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.11
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• pp.1255-1266
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• 2014

This thesis presents MPU module, Base board and sensor module which are efficient industrial control through design and manufacture as developing S5PV210 CPU of SAMSUNG used by ARM Cortex-A8 based on Android which is Open mobile platform is installed to embedded system. Data for temperature and humidity which are received by sensor module proved the suitability and validity for the real time framework design as implementing application program employed the smart phone App with hybrid application based on DB of web server.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.521-524
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• 2009

Response to nerve stimulation platform for implementing measures to detect finger movement has been functioning as an important factor. This stimulated finger on the nerve and muscle responses would vary. In other words, the finger movement of the muscle response to nerve stimulation and sensing Actuator for the H/W development is needed. In addition, a low power embedded CPU based on the top was used. H/W configuration portion of the isolation power, constant current control, High impedance INA, amplifier parts, and the stimulus mode and the Micro-control the status of current, AD converter Low Data obtained through the processing system is implemented.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.3
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• pp.145-150
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• 2014

This paper presents an effective vision based method for LED traffic light detection at the daytime. First, the proposed method calculates horizontal coordinates to set region of interest (ROI) on input sequence images. Second, the proposed uses color segmentation method to extract region of green and red traffic light. Next, to classify traffic light and another noise, shape filter and haar-like feature value are used. Finally, temporal delay filter with weight is applied to remove blinking effect of LED traffic light, and state and weight of traffic light detection are used to classify types of traffic light. For simulations, the proposed method is implemented through Intel Core CPU with 2.80 GHz and 4 GB RAM, and tested on the urban and rural road video. Average detection rate of traffic light is 94.50 % and average recognition rate of traffic type is 90.24 %. Average computing time of the proposed method is 11 ms.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.6
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• pp.367-374
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• 2022

The acceleration of neural networks has become an important topic in the field of computer vision. An accelerator is absolutely necessary for accelerating the lightweight model. Most accelerator-supported operators focused on direct convolution operations. If the accelerator does not provide GEMM operation, it is mostly replaced by CPU operation. In this paper, we proposed an optimization technique for 2-stage tiling-based GEMM routines on VTA. We improved performance of the matrix multiplication routine by maximizing the reusability of the input matrix and optimizing the operation pipelining. In addition, we applied the proposed technique to the DarkNet framework to check the performance improvement of the matrix multiplication routine. The proposed GEMM method showed a performance improvement of more than 2.4 times compared to the non-optimized GEMM method. The inference performance of our DarkNet framework has also improved by at least 2.3 times.

• The Journal of Korea Robotics Society
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• v.16 no.4
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• pp.327-335
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• 2021

In this paper, we propose an embedded robot system based on "ROS2 on Yocto" that can support various robots. We developed a lightweight OS based on the Yocto Project as a next-generation robot platform targeting cloud robotics. Yocto Project was adopted for portability and scalability in both software and hardware, and ROS2 was adopted and optimized considering a low specification embedded hardware system. We developed SLAM, navigation, path planning, and motion for the proposed robot system validation. For verification of software packages, we applied it to home cleaning robot and indoor delivery robot that were already commercialized by LG Electronics and verified they can do autonomous driving, obstacle recognition, and avoidance driving. Memory usage and network I/O have been improved by applying the binary launch method based on shell and mmap application as opposed to the conventional Python method. Finally, we verified the possibility of mass production and commercialization of the proposed system through performance evaluation from CPU and memory perspective.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.5
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• pp.267-275
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• 2017

Time of difference of arrival (TDOA) method using passive sonar sensor array has normally been used to estimate the location of a concealed moving target in underwater environment. Particle filter has been introduced for effective target estimation for non-Gaussian and nonlinear systems. In this paper, we propose a GPU-based acceleration of target position estimation using particle filter and propose efficient embedded system and software architecture. For the TDOA measurement from the passive sonar sensor, we use the generalized cross correlation phase transform (GCC-PHAT) method to obtain the correlation coefficient of the signal using FFT and we try to accelerate the calculation of GCC-PHAT based TDOA measurements using FFT with GPU CUDA. We also propose parallelization method of the target position estimation algorithm using the GPU CUDA to update the state of each particle for the target position estimation using the measured values. The target estimation algorithm was verified using Matlab and implemented using GPU CUDA. Then, we realized the proposed signal processing acceleration system using NVIDIA Jetson TX1 as the target board to analyze in terms of the execution time. The execution time of the algorithm is reduced by 55% to the CPU standalone-operation on the target board. Experiment results show that the proposed architecture is a feasible solution in terms of high-performance and area-efficient architecture.

• Journal of the Korea Society of Computer and Information
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• v.18 no.5
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• pp.9-17
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• 2013

This paper presents the design of the educational router system. This system is designed and implemented to support network configuration and embedded programming technology of the user on Internet. Not only Static routing protocol but also a kind of dynamic routing protocols such as OSPF and RIP and firewall have been programmed for education based on ethernet interface. ADS 1.2 as debugging environment, uC/OS-ii as RTOS and C language as development language are used. The educational procedures is compile, loading of static routing protocol, a kind of dynamic routing protocols such as OSPF and RIP and firewall program already supplied. Thereafter the verification is checked by using "ping" test to allow for demo operation such as hands-on training procedure. Finally programming procedure similar with demo operation of static routing protocol, a kind of dynamic routing protocols such as OSPF and RIP and packet filtering function is educated step by step.