• Title/Summary/Keyword: Electrostatic chuck (ESC)

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Fabrication of Electrostatic Chucks Using Borosilicate Glass Coating as an Insulating Layer (붕규산염 유리를 절연층으로 도포한 정전척의 제조)

  • Bang, Jae-Cheol;Lee, Ji-Hyung
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11b
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    • pp.390-393
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    • 2001
  • This study demonstrated the feasibility of tape casting method to fabricate soda borosilicate glass-coated stainless steel electrostatic chucks(ESC) for low temperature semiconductor processes. The glass coatings on the stainless steel substrates ranged from $100{\mu}m$ to $150{\mu}m$ thick. The adhesion of the glass coatings was found to be excellent such that it was able to withstand moderate impact tests and temperature cycling to over $300^{\circ}C$ without cracking and delamination. The electrostatic clamping pressure generally followed the theoretical voltage-squared curve except at elevated temperatures and higher applied voltages when deviations were observed to occur. The deviation is due to increased leakage current at higher temperature and applied voltage as the electrical resistivity drops.

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Fabrication of Electrostatic Chucks Using Borosilicate Glass Coating as an Insulating Layer (붕규산염 유리를 절연층으로 도포한 정전척의 제조)

  • 방재철;이지형
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11a
    • /
    • pp.390-393
    • /
    • 2001
  • This study demonstrated the feasibility of tape casting method to fabricate soda borosilicate glass-coated stainless steel electrostatic chucks(ESC) for low temperature semiconductor processes. The glass coatings on the stainless steel substrates ranged from 100 $\mu\textrm{m}$ to 150 $\mu\textrm{m}$ thick. The adhesion of the glass coatings was found to be excellent such that it was able to withstand moderate impact tests and temperature cycling to over 300$^{\circ}C$ without cracking and delamination. The electrostatic clamping pressure generally followed the theoretical voltage-squared curve except at elevated temperatures and higher applied voltages when deviations were observed to occur. The deviation is due to increased leakage current at higher temperature and applied voltage as the electrical resistivity drops.

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CFD Study for the Design of Coolant Path in Cryogenic Etch Chuck

  • Jo, Soo Hyun;Han, Ji Hee;Kim, Jong Oh;Han, Hwi;Hong, Sang Jeen
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.2
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    • pp.92-97
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    • 2021
  • The importance of processes in cryogenic environments is increasing in a way to address problems such as critical dimension (CD) narrow and bottlenecks in micro-processing. Accordingly, in this paper, we proceed with the design and analysis of Electrostatic Chuck(ESC) and Coolant in cryogenic environments, and present optimal model conditions to provide the temperature distribution analysis of ESC in these environments and the appropriate optimal design. The wafer temperature uniformity was selected as the reference model that the operating conditions of the refrigerant of the liquid nitrogen in the doubled aluminum path were excellent. Design of simulation (DOS) was carried out based on the wheel settings within the selected reference model and the classification of three mass flow and diameter case, respectively. The comparison between factors with p-value less than 0.05 indicates that the optimal design point is when five turns of coolant have a flow rate of 0.3 kg/s and a diameter of 12 mm. ANOVA determines the interactions between the above factor, indicating that mass flow is the most significant among the parameters of interests. In variable selection procedure, Case 2 was also determined to be superior through the two-Sample T-Test of the mean and variance values by dividing five coolant wheels into two (Case 1 : 2+3, Case 2: 3+2). Finally, heat transfer analysis processes such as final difference method (FDM) and heat transfer were also performed to demonstrate the feasibility and adequacy of the analysis process.

Investigation of Etching Characteristics for Powered Edge-Ring Utilizing PI-VM in Capacitively Coupled Argon/SF6/O2 Plasma (PI-VM을 이용한 용량 결합 Ar/SF6/O2 플라즈마에서의 전력 인가 에지 링 식각 특성 조사)

  • Hyunju Lee;Jaemin Song;Taejun Park;Nam-Kyun Kim;Gon-Ho Kim
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.4
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    • pp.7-12
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    • 2023
  • The edge ring placed on the outside of the electrostatic chuck (ESC) is a key component for protecting the ESC and controlling the etching uniformity of the edge of the wafer. Therefore, it is very important to understand the etching phenomenon of edge rings for edge ring management and equipment homeostasis. In this study, a specimen with SiO2 hard mask and underlying Si mold was installed on the edge ring surface and the etching results were measured by varying the edge ring 2MHz RF power. By developing PI-VM model with high prediction accuracy and analyzing the roles of key parameters in the model, we were able to evaluate the effect of plasma and sheath characteristics around the edge ring on edge ring erosion. This analysis method provided information necessary for edge ring maintenance and operation.

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Effects of Sintering Conditions on the Electrical Conductivity of 1 wt% Y2O3-Doped AlN Ceramics (1 wt% Y2O3 첨가계 AlN 세라믹스의 소결 조건에 따른 전기전도도)

  • Lee, Won-Jin;Lee, Sung-Min;Shim, Kwang-Bo;Kim, Hyung-Tae
    • Journal of the Korean Ceramic Society
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    • v.44 no.2 s.297
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    • pp.116-123
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    • 2007
  • Electrical properties of AlN ceramics sintered with 1 wt% $Y_2O_3$ have been investigated. From the impedance spectroscopy, electrical conductivity of grain boundary was found to be much lower than that of grain. DC conductivity measurement showed the electrode polarization effects caused by blocking electrode. The heat-treatment at $1700^{\circ}C$ of the specimen sintered at $1850^{\circ}C$ transformed continuous pain boundary phases along triple boundary junctions into isolated particles in grain comers. The heat-treatment induced decreases both in grain and grain boundary conductivity, and in DC electrical conductivities. From the analysis on the transference number, ionic conductivity was shown to be more dominant than electron conductivity, which was due to ion compensation mechanism during oxygen incorporation into grain.

In-situ Warpage Measurement Technique Using Impedance Variation (임피던스 변화를 이용한 실시간 기판 변형 측정)

  • Kim, Woo Jae;Shin, Gi Won;Kwon, Hee Tae;On, Bum Soo;Park, Yeon Su;Kim, Ji Hwan;Bang, In Young;Kwon, Gi-Chung
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.1
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    • pp.32-36
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    • 2021
  • The number of processes in the manufacture of semiconductors, displays and solar cells is increasing. And as the processes is performed, multiple layers of films and various patterns are formed on the wafer. At this time, substrate warpage occurs due to the difference in stress between each film and pattern formed on the wafer. the substrate warping phenomenon occurs due to the difference in stress between each film and pattern formed on the wafer. We developed a new warpage measurement method to measure wafer warpage during real-time processing. We performed an experiment to measure the presence and degree of warpage of the substrate in real time during the process by adding only measurement equipment for applying additional electrical signals to the existing ESC and detecting the change of the additional electric signal. The additional electrical measurement signal applied at this time is very small compared to the direct current (DC) power applied to the electrostatic chuck whit a frequency that is not generally used in the process can be selectively used. It was confirmed that the measurement of substrate warpage can be easily separated from other power sources without affecting.