• Title/Summary/Keyword: Electronics Units

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A New Complex-Number Multiplication Algorithm using Radix-4 Booth Recoding and RB Arithmetic, and a 10-bit CMAC Core Design (Radix-4 Booth Recoding과 RB 연산을 이용한 새로운 복소수 승산 알고리듬 및 10-bit CMAC코어 설계)

  • 김호하;신경욱
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.9
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    • pp.11-20
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    • 1998
  • High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

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Experimental Study on the Two Phase Thermosyphone Loop with Parallel Connected Multiple Evaporators under Partial Load and Low Temperature Operating Condition (병렬 연결된 다중 증발기 구조 2상 유동 순환형 열사이폰의 부분부하 및 저온운전 특성에 관한 실험적 연구)

  • Kang In-Seak;Choi Dong-Kyu;Kim Taig-young
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.16 no.11
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    • pp.1051-1059
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    • 2004
  • Two phase thermosyphone loop for electronics cooling are designed and manufactured to test its performance under the partial load and low environment temperature conditions. The thermosyphone device has six evaporators connected parallel for the purpose of cooling six power amplifier units (PAU) independently. The heater modules for simulating PAUs are adhered with thermal pad to the evaporator plates to reduce the contact resistance. There are unbalanced distributions of liquid refrigerant in the differently heated evaporators due to the vapor pressure difference. To reduce the vapor pressure differences caused by partial heating, two evaporators are connected each other using the copper tube. The pressure regulation tube successfully reduces these unbalances and it is good candidates for a field distributed systems. Under the low environment temperature operating condition, such as $-30^{\circ}C$, there may be unexpected subcooling in condenser. It leads the very low saturation pressure, and under this condition there exists explosive boiling in evaporator. The abrupt pressure rise due to the explosive boiling inhibits the supplement of liquid refrigerant to the evaporator for continuous cooling. Finally the cooling cycle will be broken. For the normal circulation of refrigerant there may be an optimum cooling air flow rate in condenser to adjust the given heat load.

High-Performance Line-Based Filtering Architecture Using Multi-Filter Lifting Method (다중필터 리프팅 방식을 이용한 고성능 라인기반 필터링 구조)

  • 서영호;김동욱
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.75-84
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    • 2004
  • In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

An Improvement of Digital Distance Relaying Algorithm on Underground Transmission Cables (지중송전케이블룡 디지털 거리계전 알고리즘 개선)

  • Ha, Che-Ung;Lee, Jong-Beom
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.49 no.12
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    • pp.595-601
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    • 2000
  • This paper describes the improvement method of distance relaying algorithm for the underground transmission cables. Distance relaying algorithms have been mainly developing to protect the overhead transmission lines than the underground cables. If the cable systems are directly protected using distance relaying algorithm developed for overhead line without any improvement, there will be really occurred many misoperation in cable systems, because the cable systems consist of the conductor, the sheath, several grounding method, cable cover protection units(CCPUs), and grounding wire. Accordingly, the complicated phenomena are occurred, if there is a fault in cable systems. Therefore, to develope a correct distance relaying algorithm, such cable characteristics should be taken into account. This paper presents the process to improve distance relaying algorithm which is now used. REal cable system was selected to establish modeling in EMTP and ATP Draw. It was discovered through the detailed simulation during the fault that the large error existed between impedance measured at the relay point and real impedance is due to the resistance of grounding wire in each grounding method. And also compensation factor obtained by the simulation is proposed in this paper. It is proved that the factor proposed can fairly improve the accuracy of impedance at the relay point. It is evaluated that the protective ability will be really much improved, if the algorithm proposed in this paper is applied for cable systems of utility.

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Isoindigo Based Small Molecules for High-Performance Solution-Processed Organic Photovoltaic Devices

  • Elsawy, W.;Lee, C.L.;Cho, S.;Oh, S.H.;Moon, S.H.;Elbarbary, A.;Lee, Jae-Suk
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.245.2-245.2
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    • 2013
  • Solution processed organic photovoltaic devices have relatively less attention compared to polymer photovoltaic devices even though they have high possibility to be developed because they have both advantages of polymer and organic, such as solution processable, no synthetic batch dependence of photovoltaic performance, high purity and high charge carrier mobility as well as relatively high efficiency (~7%). In addition, solution processed organic photovoltaic devices have an advantage of easiness to study the relationship between the molecular structure and photovoltaic performance due to its simple structure. In this work, five isoindigo based low band gap donor-acceptor-donor (D-A-D) small molecules with different electron donating strength were synthesized for investigating the relationship between the molecular structure and photovoltaic performance, especially, investigating the effects of different electron donating effect of donor group in isoindigo backbone to photovoltaic device performance. The variation of electron donating strength of donor group strongly affected the optical, thermal, electrochemical and photovoltaic device performances of isoindigo organic materials. The highest power conversion efficiency of ~3.2% was realized in bulk heterojuction photovoltaic device consisted of the ID3T as donor and PC70BM as acceptor. This work demonstrates the great potential of isoindigo moieties as electron deficient units as well as guideline for synthesis of donor-acceptor-donor (D-A-D) small molecules for realizing highly efficient solution processed organic photovoltaic devices.

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Technical Trends of AI Military Staff to Support Decision-Making of Commanders (지휘관들의 의사결정지원을 위한 AI 군참모 기술동향)

  • Lee, C.E.;Son, J.H.;Park, H.S.;Lee, S.Y.;Park, S.J.;Lee, Y.T.
    • Electronics and Telecommunications Trends
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    • v.36 no.1
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    • pp.89-98
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    • 2021
  • The Ministry of National Defense aims to create an environment in which transparent and reasonable defense policies can be implemented in real time by establishing the vision of smart defense innovation based on the Fourth Industrial Revolution and promoting innovation in technology-based defense operation systems. Artificial intelligence (AI) based defense technology is at the level of basic research worldwide, includes no domestic tasks, and involves classified military operation data and command control/decision information. Further, it is needed to secure independent technologies specialized for our military. In the army, military power continues to decline due to aging and declining population. In addition, it is expected that there will be more than 500,000 units should be managed simultaneously, to recognize the battle situation in real time on the future battlefields. Such a complex battlefield, command decisions will be limited by the experience and expertise of individual commanders. Accordingly, the study of AI core technologies supporting real-time combat command is actively pursued at home and abroad. It is necessary to strengthen future defense capabilities by identifying potential threats that commanders are likely to miss, improving the viability of the combat system, ensuring smart commanders always win conflicts and providing reasonable AI digital staff based on data science. This paper describes the recent research trends in AI military staff technology supporting commander decision-making, broken down into five key areas.

Lightweight FPGA Implementation of Symmetric Buffer-based Active Noise Canceller with On-Chip Convolution Acceleration Units (온칩 컨볼루션 가속기를 포함한 대칭적 버퍼 기반 액티브 노이즈 캔슬러의 경량화된 FPGA 구현)

  • Park, Seunghyun;Park, Daejin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.11
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    • pp.1713-1719
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    • 2022
  • As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms.

Application of Fault Location Method to Improve Protect-ability for Distributed Generations

  • Jang Sung-Il;Lee Duck-Su;Choi Jung-Hwan;Kang Yong-Cheol;Kang Sang-Hee;Kim Kwang-Ho;Park Yong-Up
    • Journal of Electrical Engineering and Technology
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    • v.1 no.2
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    • pp.137-144
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    • 2006
  • This paper proposes novel protection schemes for grid-connected distributed generation (DG) units using the fault location algorithm. The grid-connected DG would be influenced by abnormal distribution line conditions. Identification of the fault location for the distribution lines at the relaying point of DG helps solve the problems of the protection relays for DG. The proposed scheme first identifies fault locations using currents and voltages measured at DG and source impedance of distribution networks. Then the actual faulted feeder is identified, applying time-current characteristic curves (TCC) of overcurrent relay (OCR). The method considering the fault location and TCC of OCR might improve the performance of the conventional relays for DG. Test results show that the method prevents the superfluous operations of protection devices by discriminating the faulted feeder, whether it is a distribution line where DG is integrated or out of the line emanated from the substation to which the DGs are connected.

Efficient Token Flow Design for the MPEG RMC Framework

  • Cui, Li;Kim, Sowon;Kim, Hyungyu;Jang, Euee S.
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.5
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    • pp.251-258
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    • 2014
  • This paper proposes an efficient token flow design methodology for a decoder in the MPEG Reconfigurable Media Coding (RMC) framework. The MPEG RMC framework facilitates a decoder to be configured with a set of modules called functional units (FUs) that are connected by tokens. Such a modular design philosophy of the MPEG RMC framework enables the reusability and reconfigurability of FUs. One drawback of the MPEG RMC framework is that the decoder performance can be affected by increasing the token transmissions between FUs. The proposed method improves the design of the FU network in the RMC framework toward real-time decoder implementation. In the proposed method, the merging of FU, the separation of token flow, and the merging of token transactions are applied to minimize the token traffic between FUs. The experimental results of the MPEG-4 SP decoder show that the proposed method reduces the total decoding time by up to 77 percent compared to the design of the RMC simulation model.

Unit Generation Based on Phrase Break Strength and Pruning for Corpus-Based Text-to-Speech

  • Kim, Sang-Hun;Lee, Young-Jik;Hirose, Keikichi
    • ETRI Journal
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    • v.23 no.4
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    • pp.168-176
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    • 2001
  • This paper discusses two important issues of corpus-based synthesis: synthesis unit generation based on phrase break strength information and pruning redundant synthesis unit instances. First, the new sentence set for recording was designed to make an efficient synthesis database, reflecting the characteristics of the Korean language. To obtain prosodic context sensitive units, we graded major prosodic phrases into 5 distinctive levels according to pause length and then discriminated intra-word triphones using the levels. Using the synthesis unit with phrase break strength information, synthetic speech was generated and evaluated subjectively. Second, a new pruning method based on weighted vector quantization (WVQ) was proposed to eliminate redundant synthesis unit instances from the synthesis database. WVQ takes the relative importance of each instance into account when clustering similar instances using vector quantization (VQ) technique. The proposed method was compared with two conventional pruning methods through objective and subjective evaluations of synthetic speech quality: one to simply limit the maximum number of instances, and the other based on normal VQ-based clustering. For the same reduction rate of instance number, the proposed method showed the best performance. The synthetic speech with reduction rate 45% had almost no perceptible degradation as compared to the synthetic speech without instance reduction.

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