• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.12
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• pp.919-923
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• 2010

Copper pillar tin bump (CPTB) was developed for high density chip interconnect technology. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM -1250 dry film photoresist (DFR), copper electroplating method and Sn electro-less plating method. Mechanical shear strength measurements were introduced to characterize the bonding process as a function of thermo-compression. Shear strength has maximum value with $330^{\circ}C$ and 500 N thenno-compression process. Through the simulation work, it was proved that when the copper pillar tin bump decreased in its size, it was largely affected by the copper oxidation.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.280-288
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• 2016

Microelectronic product consumers may already be expecting another paradigm shift with smarter phones over smart phones, but the current status of microelectronic manufacturing engineering education (MMEE) in universities hardly makes up the pace for such a fast moving technology paradigm shift. The purpose of MMEE is to educate four-year university graduates to work in the microelectronics industry with up-to-date knowledge and self-motivation. In this paper, we present a comprehensive curriculum for a four-year university degree program in the area of microelectronics manufacturing. Three hands-on experienced-based courses are proposed, along with a methodology for undergraduate students to acquire hands-on experience, towards integrated circuits (ICs) design, fabrication and packaging, are presented in consideration of manufacturing engineering education. Semiconductor device and circuit design course for junior level is designed to cover how designed circuits progress to micro-fabrication by practicing full customization of the layout of digital circuits. Hands-on experienced-based semiconductor fabrication courses are composed to enhance students’ motivation to participate in self-motivated semiconductor fab activities by performing a series of collaborations. Finally, the Microelectronics Packaging course provides greater possibilities of mastered skillsets in the area of microelectronics manufacturing with the fabrication of printed circuit boards (PCBs) and board level assembly for microprocessor applications. The evaluation of the presented comprehensive curriculum was performed with a students’ survey. All the students responded with “Strongly Agree” or “Agree” for the manufacturing related courses. Through the development and application of the presented curriculum for the past six years, we are convinced that students’ confidence in obtaining their desired jobs or choosing higher degrees in the area of microelectronics manufacturing was increased. We confirmed that the hypothesis on the inclusion of handson experience-based courses for MMEE is beneficial to enhancing the motivation for learning.

• Journal of Mechanical Science and Technology
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• v.14 no.2
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• pp.251-258
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• 2000

Thermal deformation in an electronic package due to thermal strain mismatch is investigated. The warpage and the in-plane deformation of the package after encapsulation is analyzed using the laminated plate theory. An exact solution for the thermal deformation of an electronic package with circular shape is derived. Theoretical results are presented on the effects of the layer geometries and material properties on the thermal deformation. Several applications of the exact solution to electronic packaging product development are illustrated. The applications include lead on chip package, encapsulated chip on board and chip on substrate.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.9-15
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• 2020

The 'field-effect' underlies the operation of most conventional electronic devices. However, effective control and implementation of the field-effect in semiconductor devices are limited due to screening of the electric-field by conducting electrodes. Thus far, the electronic devices have necessarily been designed to avoid or minimize the electric-field screening effect. As an alternative approach to this, a new type of conducting electrodes which would be transparent to both visible light and electric-field while being electrically conductive have been developed. Here, we define these electrodes as 'electric-field transparent electrodes' and provide a review on related work. Particular attention is paid to the material selection and design strategies to enhance the electric-field transparency of the electrodes while maintaining good electrical conductivity and optical transparency. We then introduce potential applications of the electric-field transparent electrodes in electronic and optoelectronic devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.57-62
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• 2008

From the progressing results, it was found that thin film using 52 wt% Ni - 38 wt% Cr - 3 wt% Al - 4 wt% Mn - 3 wt% Si target has good characteristics for low TCR (temperature coefficients of resistance) and high resistivity. The optimum sputtering condition was DC 250 W, 5 mtorr, and 50 sccm and the proper annealing condition was $350^{\circ}C$/3.5 hr in air atmosphere. At these fabricated conditions, thin film resistors with TCR values of less than ${\pm}10ppm/^{\circ}C$ were obtained. The TCR of the packaged-samples made at proper fabrication conditions was $-3{\sim}15ppm/^{\circ}C$ after the thermal cycling and $-20{\sim}180ppm/^{\circ}C$ after PCT (pressure cooker test), we could confirm reliability for the thin film resistor and find the need for enduring research about packaging method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.220-223
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• 1996

Mechanical properties of Plasma-Enhanced Chemical Vapor Deposited (PECVD) silicon nitride thin film was studied to determine the feasibility of the film as a passivation layer over the aluminum bonding areas of integrated circuit chips. Ultimate strain of the films in thicknesses of about 5 k${\AA}$ was measured using four-point bending method. The ultimate strain of these films was constant at about 0.2% regardless of residual stress. Intrinsic and residual stresses of these films were measured and compared with thermal shock and cycling test results. Comparison of the results showed that more tensile films were more susceptible to crack- induced failure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.442-446
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• 1999

Melting behavior and bridge phenomenon of solder paste, which is essential for surface mount technology in packaging, were investigated. solder paste of Sn-37%Pb was printed on Sn-coated Cu-pattern of PCB, and heated over melting point. Melting behavior of the paste was observed using CCD-camera. In order to modelize the melting and agglomeration phenomena of the paste, two solder balls of 0.76mm diameter were used. As experimental results, the paste start to melt from the margin of the printed shape. The hight of the melted paste decreased from 270 $\mu$m to 200 $\mu$m firstly, and finally recovered to 250 $\mu$m. During the melting procedure, pores were evolved from the molten paste. Bridge Phenomenon of the molten Paste depends upon the pitch of the pattern.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.76-79
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• 2003

The characteristic of single wall carbon nanotube (SW-CNT) and herringbone nano fiber (HB-CNF) emitters was described. SW-CNT synthesized by arc discharge and HB-CNF prepared by thermal CVD were mixed with binders and conductive materials, and then were formed by screen-printing process. In order to obtain efficient field emissions, the surface treatment of rubbing & peel-off was applied to the printed CNT and CNF emitters. The basic structure of FED was of a diode type through fully vacuum packaging. Also, we proposed a new triode type of field emitter using a mesh gate plate having tapered holes and could achieve the ideal triode properties with no gate leakage currents.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.39-43
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• 2011

Effects of cavity material on the Q-factor measurement of microwave dielectric materials were studied by HFSS simulation and the measurements using metal cavity. $TE_{01\delta}$ mode resonant frequency was determined from the electric and magnetic field patterns and the loaded Q-factor was calculated from 3dB bandwidth of $S_{21}$ spectrum. When the cavity metal materials were Cu, SUS and Au cavity, the level of Q-factor was similar. However, Q-factor was significantly decreased when the cavity metal material was CuO. The Q-factor measurements of dielectric resonator by network analyzer using various metal cavity exhibits consistent behavior.