• 제목/요약/키워드: Electronic devices

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Electrical Properties of MOS Devices by Rapid Thermal Nitridation(RTN) (RTN에 의해 제작된 MOS소자의 전기적 특성)

  • Chang, Eui-Gu;Choi, Won-Bun;Lee, Cheol-In
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1988.05a
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    • pp.24-26
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    • 1988
  • The electrical properties of thin nitrided thermal oxides prepared by rapid thermal nitridation(RTN) have been studied. The flatband voltages were calculated using C-V measurement and found to vary as nitridation time and temperature. After nitridation an increase in the fixed oxide charge density was always observed, but the distribution of it as a function of annealing time was found to be random. The breakdown voltages were measured using curve tracer.

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Etching characteristics of ZnS:Mn thin films using $BCl_3/Ar$ high density plasma ($BCl_3/Ar$ 고밀도 플라즈마를 이용한 ZnS:Mn 박막의 식각 특성)

  • Kim, Gwan-Ha;Kim, Chang-Il;Lee, Cheol-In;Kim, Tae-Hyung
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.124-125
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    • 2005
  • ZnS:Mn thin films have attracted great interest as electroluminescence devices. In this study, inductively coupled BCl$_3$/Ar plasma was used to etch ZnS:Mn thin films. We obtained the maximum etch rate of ZnS:Mn thin films was 2209 ${\AA}$/min at a BCl$_3$(20%)/Ar(80%) gas mixing ratio, an RF power of 700 W, a DC bias voltage of-250 V, a total gas flow of 20 sccm, and a chamber pressure of 1 Pa. It was proposed that sputter etching is dominant etching mechanism while the contribution of chemical reaction is relatively low due to low volatility of etching products.

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Laser annealing on ZnO:P thin films (ZnO:P 박막의 레이저 어닐링 연구)

  • Chang, Hyun-Woo;Kang, Hong-Seong;Kim, Gun-Hee;Lim, Sung-Hoon;Lee, Sang-Yeol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.51-52
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    • 2005
  • Phosphorus doped ZnO thin films on (001) $Al_2O_3$ substrate have been prepared by a pulsed laser deposition (PLD) technique using a Nd:YAG laser. After deposition, phosphorus doped ZnO thin films have been annealed in vacuum, air, nitrogen, and oxygen ambients using pulsed Nd:YAG laser. We report the electrical properties of phosphorus doped ZnO thin films with the variation of the laser annealing conditions for the applications of optoelectronic devices.

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Polarity Control of Wurtzite Crystal by Interface Engineering (계면공학에 기초한 우르차이트 결정의 극성 조절)

  • Hong, Soon-Ku;Suzuki, Takuma;;Cho, Myung-Whan;Yao, Takafumi
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.95-96
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    • 2005
  • The general method and mechanism for the polarity control of heteroepitaxial wurtzite films, such as ZnO and GaN, by interface engineering via plasma-assisted molecular beam epitaxy are addressed. We proposed the principle and method controlling the crystal polarity of ZnO on GaN and GaN on ZnO. The crystal polarity of the lower film was maintained by forming a heterointerfce without any interface layer between the upper and the lower layers. However the crystal polarity could be changed by forming the heterointerface with the interface layer having an inversion center. The principle and method suggested here give us a promising tool to fabricate polarity inverted heterostructures, which applicable to invent novel heterostructures and devices.

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A study on the programming conditions suppressing the lateral diffusion of charges for the SONOS two-bit memory (SONOS two-bit 메모리의 측면확산에 영향을 주는 programming 조건 연구)

  • Lee, Myung-Shik;An, Ho-Myung;Seo, Kwang-Yell;Koh, Jung-Hyuk;Kim, Byung-Cheul;Kim, Joo-Yeon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.117-120
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    • 2005
  • The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

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Analysis on Proecwss Characteristics of 2'nd Silicidation Formation Process at MOS Structure (MOS 구조에서 실리사이드 형성단계의 공정특성 분석)

  • Eom, Gum-Yong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.130-131
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    • 2005
  • In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

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A study on the Dislocation-Free Shallow Trench Isolation (STI) Process (Dislocation-Free Shallow Trench Isolation 공정 연구)

  • Yoo, Hae-Young;Kim, Nam-Hoon;Kim, Sang-Yong;Lee, Woo-Sun;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.84-85
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    • 2005
  • Dislocations are often found at Shallow Trench Isolation (STI) process after repeated thermal cycles. The residual stress after STI process often leads defect like dislocation by post STI thermo-mechanical stress. Thermo-mechanical stress induced by STI process is difficult to remove perfectly by plastic deformation at previous thermal cycles. Embedded flash memory process is very weak in terms of post STI thermo-mechanical stress, because it requires more oxidation steps than other devices. Therefore, dislocation-free flash process should be optimized.

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Electrical Strength of the Insulating Materials for High-Tc Superconducting Devices

  • Bae, Duck-Kweon;Kim, Chung-Hyeok;Oh, Yong-Cheul;Kim, Jin-Sa;Shin, Cheol-Gee;Song, Min-Jong;Lee, Joon-Ung
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.149-150
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    • 2005
  • According to the trend for electric power equipment of high capacity and reduction of its size, the needs for the new high performance electric equipments become more and more important. On of the possible solution is high temperature superconducting (HTS) power application. Following the successful development of practical HTS wires, there have been renewed activities in developing superconducting power equipment. HTS equipments have to be operated in a coolant such as liquid nitrogen ($LN_2$) or cooled by conduction-cooling method such as using Gifford-McMahon (G-M) cryocooler to maintain the temperature below critical level. In this paper, the dielectric strength of unfilled epoxy and filled epoxy in $LN_2$ was analyzed. The filled epoxy composite not only compensates for this fragile property but enhances its dielectric strength.

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Optoelectronic Characteristics of Hydrogen and Oxygen Annealed Si-O Superlattice Diode

  • Seo, Yong-Jin
    • Transactions on Electrical and Electronic Materials
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    • v.2 no.2
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    • pp.16-20
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    • 2001
  • Optoelectronic characteristics of the superlattice diode as a function of deposition temperature and annealing conditions have been studied. The multilayer nanocrystalline silicon/adsorbed oxygen (nc/Si/O) superlattice formed by molecular beam epitaxy (MBE) system. Experimental results showed that deposition temperature of 550$^{\circ}C$, followed by hydrogen annealing leads to best results, in terms of optical photoluminescence (PL) and electrical current-voltage (I-V) characteristics. Consequently, the experimental results of multilayer Si/O superlattic device showed the stable photoluminescence and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic devices, and can be readily integrated with conventional silicon ULSI processing.

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The Degradations of Effective Mobility in Surface Channel MOS Devices (표면 채널 모스 소자에서 유효 이동도의 열화)

  • 이용재;배지칠
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1996.05a
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    • pp.51-54
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    • 1996
  • This paper reports the studies of the inversion layer mobility in p-channel Si MOSFET's under hot-carrier degradated condition. The validity of relationship of hot carrier degradations between the surface effective mobility and field effect mobility and are examined. The effective mobility(${\mu}$$\_$eff/) is derived from the channel conductances, while the field-effect mobility(${\mu}$$\_$FE/) is obtained from the transconductance. The characteristics of mobility curves can be divided into the 3 parts of curves. It was reported that the mobility degradation is due to phonon scattering, coulombic scattering and surface roughness. We are measured the mobility slope in curves with DC-stress [V$\_$g/=-3.1v]. It was found that the mobility(${\mu}$$\_$eff/ and ${\mu}$$\_$FE/) of p-MOSFET's was increased by increasing stress time and decreasing channel length. Because of the increasing stress time and increasing V$\_$g/ is changed oxide reliability and increased vertical field.

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