• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.828-831
• /
• 2001

A simple and versatile method of manufacturing semiconductor devices with pn-junctions used the silicon direct bonding technology with simultaneous impurity diffusion is suggested . Formation of p- or n- type layers was tried during the bonding procedure by attaching two wafers in the aqueous solutions of Al(NO$_3$)$_3$, Ga(NO$_3$)$_3$, HBO$_3$, or H$_3$PO$_4$. An essential improvement of bonding interface structural quality was detected and a model for the explanation is suggested. Diode, Dynistor, and BGGTO structures were fabricated and examined. Their switching characteristics are presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.848-850
• /
• 2001

In this work, we investigated on the white-colored ribbon fiber synthesized from GaN powder. We convinced the formation of monoclinic phase $\beta$-Ga$_2$O$_3$from the X-ray diffraction pattern on ribbon fiber. The 10 K PL spectrum consisted with the strong emission band caused by self-activated optical center at 3.464 eV with the full-width at half maximum of 48 meV and the impurity related emission bands. Through this work, the optical properties and the electrical conductivity of $\beta$-Ga$_2$O$_3$, it will be useful for the fabrication of optoelctronic devices operating in visible spectrum region.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.874-877
• /
• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.343-346
• /
• 2001

To implementation of white electroluminescnet device in this paper, two methods were tried without synthesis of new white EL phosphor. At first, ZnS:Mn,Cl was mixed with ZnS:Cu from 20 to 50 weight percents. Second, ZnS:Mn,Cl was mixed with blue dye from 0 to 1.2 weight percents. The devices for experiments were measured as following; current-voltage, emission spectrum, brightness-voltage and CIE coordinate system and frequency properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.358-360
• /
• 2001

In this study, the bis(8-oxyquinolino)zinc II (Znq$_2$) were synthesized successfully from zinc chloride (ZnC1$_2$) as a initial material. Then, we fabricated red organic electroluminescent device with a dye (DCJTB)-doped and inserted Znq$_2$ between emission layer and cathode layer for increasing EL efficiency. The hole transfer layer is a N,N'-diphenyl-N,N'-bis-(3-methyl phenyl) -1,1'-diphenyl-4,4'- diamine(TPD), and the host material of emission layer is Znq$_2$. And we study the electrical and optical properties of devices. We found that the device using Znq$_2$ inserting layer result in the increased efficiency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.628-631
• /
• 2001

Current lead is one of the first proposed devices for the application of High Temperature-Superconductor(HTSC). The current lead provides high current for electrical machine using superconductor from room temperature. Its characteristics that is zero resistance and low heat transfer rate under critical temperature lead to research for the replacement of existing current lead with HTSC. In this paper, we investigated the temperature distributions of stacking type and rod type current lead with each cross-section area and length using Nastran program and compared each temperature distribution. It is obtained from this paper that stacking type current lead has flat temperature gradient and than rod type one and more stable operation as current lead is closely related with its cross-section area and length.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.447-450
• /
• 2001

Abstract-Si direct bonding(SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera, respectively. Components existed in the interlayer were analysed by using FT-lR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 2.4kgf/cm$^2$∼Max : 14.9kgf/cm$^2$).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.335-338
• /
• 1998

Ferroelectric Sr$_2$(Nb,Ta)$_2$O$_{7}$ (SNTO) thin films were prepared by chemical solution deposition processes. SNTO thin films were spin-coated on Pt/Ti/SiO$_2$/(100)Si substrates. After multiple coating, dried thin films were heat-treated for decomposition of residual organics and crystallization. B site-rich impurity phase, i.e. [Sr(Nb,Ta)$_2$O$_{6}$], was found after annealing, where its appearance was dependent on process temperature indicating the possible reaction with substrate. Dielectric and other relevant electrical properties were measured and the results showed a little possibility in ferroelectric gate random access memory devices.s.s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.151-154
• /
• 1998

We have investigated a correlation of the electrical properties of the Pd/Ge/Pd/Ti/Au ohmic contact on n-InGaAs with its microstructures for the high temperature application of compound semiconductor devices. The samples were heat-treated by the rapid thermal annealing at various temperatures. In the contact system, moderately good specific contact resistance was obtained even before annealing because of the low metals-InGaAs barrier height, and better ohmic performances were observed by annealing up to 400˚C. But the ohmic performance was degraded after annealing at 450˚C due to the increment of Pd$_2$Ga$\sub$5/ phases.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.4
• /
• pp.321-326
• /
• 2005

Chemical mechanical polishing(CMP) process is essential technology to be applied to manufacturing the dielectric layer and metal line in semiconductor devices. It has been known that overpolishing in CMP depends on pattern selectivity as a function of density and pitch, and use of fixed abrasive pad(FAP) is one method which can improve the pattern selectivity. Thus, dishing & erosion defects can be reduced. This paper introduces the manufacturing technique of FAP using hydrophilic polymers with swelling characteristic in water and explains the self-conditioning phenomenon. When applied to tungsten blanket wafers, the FAP resulted in appropriate performance in point of uniformity, material selectivity and roughness. Especially, reduced dishing and erosion was observed in CMP of tungsten pattern wafer with the proposed FAP.