• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• Resources Recycling
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• v.25 no.1
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• pp.24-30
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• 2016

The study to obtain tantalum concentration from electronic components (ECs) on Printed circuit board assembly (PCBA) of laptop was conducted. Electronic components on laptop PCBA were detached from boards by using self-developed experimental apparatus. The detached electronic components were sieved and 93.2 wt.% of tantalum capacitors were concentrated from the size interval from 2.80 mm to 6.35 mm. The tantalum capacitors were pulverized by hammer mill and electrodes (anode and cathode) were removed from the grinding products by using magnetic separators under the magnetic force of 300 Gauss. Finally, tantalum concentrate was concentrated from the magnetic separator products by using Knelson concentrator, and the maximum efficiency of 76.9% was achieved under the operating condition of bowl rotating speed of 200 rpm, and fluidizing water flowrate of 7 L/min. The grade and recovery of Ta concentrate under the condition were 81.1% and 78.8%, respectively.