• 대한전자공학회논문지SD
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• 제46권10호
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• pp.16-24
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• 2009

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET는 기존의 DG-MOSFET의 3-terminal 소자구조가 갖고 있는 한계에서 벗어나 front-gate와 back-gate를 서로 다른 전압으로 구동하는 것이 가능하다. IGM-DG를 이용함으로써 4번째 단자의 자유도에 의해 회로설계가 간단해 질 뿐 아니라, 집적도를 향상시킬 수 있는 장점을 가진다. 본 논문에서는 IGM-DG MOSFET를 사용하여 RF 수신단을 설계하였고, HSPICE 시뮬레이션을 통해 회로성능을 검증하고 소자의 특성변화에 따른 최적의 회로설계 방향을 제시하였다.

• 센서학회지
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• 제25권5호
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• pp.326-332
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• 2016

A novel CMOS temperature sensor with binary output is implemented by using fully differential switched-capacitor circuits for resistorless implementation of the temperature sensor core. Temperature sensing is based on the temperature characteristics of the pn diodes implemented by substrate pnp transistors fabricated using standard CMOS processes. The binary outputs are generated by using the charge-balance principle that eliminates the division operation of the PTAT voltage by the bandgap reference voltage. The chip was designed in a MagnaChip $0.35-{\mu}m$ CMOS process, and the designed circuit was verified using Spectre circuit simulations. The verified circuit was laid out in an area of $950{\mu}m{\times}557 {\mu}m$ and is currently under fabrication.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.189-192
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• 2001

This paper proposed that an AC-DC converter system using multiple buck-chopper operates with four choppers connecting to a number of parallel circuits. To improve these, a large number of soft switching topologies included a resonant circuit have been proposed. And, some simulative results on computer are included to confirm the validity of the analytical results. The partial resonant circuit makes use of an inductor using step-down and a condenser of loss-less snubber. The result is that the switching loss is very low and the efficiency of system is high. And the snubber condenser used in a partial resonant circuit makes charging energy regenerated at input power source for resonant operation. The proposed conversion system is deemed the most suitable for high power applications where the power switching devices are used.

• ETRI Journal
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• 제30권5호
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• pp.729-734
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• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 추계학술대회 논문집
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• pp.149-152
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• 2001

A Single-phase bi-directional inverter Using a diode bridge-type resonant circuit to implement ZVT(Zero Voltage Transition) switching is Presented. It is shown that the ZACE(Zero Average Current Error) algorithm based polarized ramptime current control can provide a suitable interface between diode bridge-type resonant circuit DC link and the inverter. The current control algorithm is analyzed about how to design the circuit with analyzed switch which m ZVT operation for the main power switch The simulation and experimental results would be shown to verify the proposed current algorithm, because the main power switch is turn on with ZVT and the bi-directional inverter is operated.

• Journal of Electrical Engineering and Technology
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• 제10권6호
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• pp.2334-2342
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• 2015

This paper proposes an LED driving circuit with a digital controller, power factor correct (PFC) function, and low light flicker. The key topology of the proposed circuit is a conventional Flyback combined with a pre-stage. As a result, there will be less light flicker than with other one-stage PFC circuits. A digital controller, implemented using a low-cost microcontroller, dsPIC30F2020, will meet PFC and low light flicker. The experimental results validate the functionality of the proposed circuit.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.373-376
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• 2001

When varistors for circuit protection is used at high voltage, it's operation properties were unstable because of leakage current and nonlinear coefficient with grain size. For the purpose of improving of ZnO varistor properties, high voltage ZnO varistor was fabricated with Y$_2$O$_3$addition. Electrical properties were investigated according to sintering conditions and mixing conditions. ZnO varistors was shown ohmic Properties when it's applied voltage was below critical voltage. It was shown non-ohmic properties over critical voltage, because current was increased with decreasing resistance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2798-2800
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• 1999

A new circuit, modified valley fill (MVF) combined with resonant inductor of the self-excited resonant inverter and charge pump capacitors(CPCs), is presented to achieve high PF electronic ballast providing sufficient preheat current to lamp filaments for soft start maintaining low DC bus voltage. The MVF can adjust the valley voltage higher than half the peak line voltage. The CPCs draw the current from the input line to make up the current waveform during the valley interval. The measured PF and THD are 0.99 and 12%, respectively. The lamp current CF is also acceptable in the proposed circuit. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.360-363
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• 1999

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.