• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.9
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• pp.1070-1074
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• 2014

According to IEEE 1662(2009), IPS is a power system where all prime movers produce electrical power that is shared among propulsion, mission, and ship service loads. Discriminating attributes of integrated power systems are flexibility of movers' arrangements, mechanical decoupling between prime movers and propulsors, an increased level of energy conversion and transmission redundancy, and flexibility of redistributing available electrical power for future electronic weapons. IPS could have various steps of power that can be produced at optimal load of movers. In this study, an evaluation method for optimal arrangement of movers was investigated when an IPS warship is projected. The two factors are utilized for the quantitative analysis which are the weight of system as the fighting power and the fuel consumption per year as the economic feasibility. And also the ways for arrangement of system were studied according to existence of small diesel generator. The evaluation method that decides the optimization level is based on the DEA(Data Envelopment Analysis)

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.564-569
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• 2012

This paper proposes a hybrid-excited linear synchronous motor (LSM) that has potential applications in a magnetically levitated vehicle. The levitation and thrust force characteristics of the LSM are investigated by means of three-dimensional (3-D) numerical electromagnetic FEM calculations and experimental verification. Compared to a conventional LSM with electromagnets, a hybrid-excited LSM can improve levitation force/weight ratios, and reduce the power consumption of the vehicle. Because the two-dimensional (2-D) FE analysis model describes only the center section of the physical device, it cannot express the complex behavior of leakage flux, which this study is able to predicts along with levitation and thrust force characteristics by 3-D FEM calculations. A static force tester for a hybrid-excited LSM has been manufactured and tested in order to verify these predictions. The experimental results confirm the validity of the 3-D FEM calculation scheme for the description of a hybrid-excited LSM.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.15 no.1 s.94
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• pp.105-111
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• 2005

This paper is concerned with the active vibration control of smart structure using actuator signal made of pulse width modulation. The pulse width modulation has been used in motor control, where the amount of energy fed into the motor is controlled by the pulse width instead of applied voltage. The advantage of using the pulse width modulation is that analog signal can be replaced by the digital signal so that we can reduce system costs and power consumption. The effect of pulse width modulation on the vibration response was investigated in this study and the valid transformation rule was found. Then, the pulse width modulation was realized using a microprocessor and electronic circuit. The active vibration suppression was carried out by combining the positive position feedback controller and the pulse width modulation. The experimental result shows that we can replace an expensive amplifier with a pulse width modulation system thus reducing the system cost. The result also shows that the active vibration control can be achieved by the pulse width modulation technique.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1308-1312
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• 2011

CCFL(Cold Cathode Fluorescent Lamp)for BLU of LCD and special lighting has been widely utilized. The removal of oxide film formed on electrode of CCFL in manufacturing process is required. In this pape Plasma treatment was carried out to remove the oxide film. To ensure the optimum process, the analysis of sheet resistance, XRD, AFM and solder test was conducted. A minimum sheet resistance and the maximum percentage of the solder coverage ratio were measured in optimal process conditions such as plasma power consumption 600W and processing time of 70 seconds. As the plasma treatment is confirmed to be due to removal of copper oxide, this process is expected to be used as a treatment of electrode for CCFL.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.3
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• pp.153-157
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• 2011

This study to implement properties such as high brightness, reliability, lower power consumption and long lifetime indoor illumination control visible light communication system that with LED used by illuminations. It has probability presently to apply many application field like ubiquitous. To implement such a system, it designs Date to transmit signals to visible light communication transmitter/receiver analyzes the communication performance using computer programming language. This research result Confirmed that it is possible to implement indoor illumination control visible light communication transmitter/receiver consisting of smooth date.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.2
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• pp.840-845
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• 2013

In this paper, the broadband frequency double down-converter based on LC filter technologies has been designed and implemented, and its performances are introduced. The Designed frequency double down-converter is consisted with a low-noise amplifier, mixer, IF amplifier, LC filter, DC-block capacitor and RF-bypass capacitor. Especially, instead of active devices of a typical converter, the suggested converter designed using passive devices to provide both low-power consumption and low-cost model. As results of the measurement, the implemented frequency double down-converter realizes the broadband performance with the bandwidth of 100MHz (13~113MHz) at the center frequency of 63MHz, and its gain is approximately 40dB.