• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.6
• /
• pp.568-574
• /
• 2020

In this paper, we propose a method to reduce the square root computation having high computation complexity in Canny edge detection algorithm using image processing. The proposed method is to reduce the number of operation calculating gradient magnitude using pixel's continuity using make a specific pattern instead of square root computation in gradient magnitude calculating operation. Using various test images and changing number of hole pixels, we can check for calculate match rate about 97% for one hole, and 94%, 90%, 88% when the number of hole is increased and measure decreasing computation time about 0.2ms for one hole, and 0.398ms, 0.6ms, 0.8ms when the number of hole is increased. Through this method, we expect to implement low power embedded vision system through high accuracy and a reduced operation number using two-hole pixels.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.39-50
• /
• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.60-68
• /
• 2010

In case of sensorineural hearing loss, auditory perception can be activated by electrical stimulation of the nervous system via electrode implanted into the cochlea or auditory nerve. Since the tonotopic map of the human auditory nerve has not been definitively identified, the recording of auditory nerve signal with microelectrode is desirable for determining the tonotopic map. This paper proposes the multi-channel analog front-end for auditory nerve signal detection. A channel of the proposed analog front-end consists of an AC coupling circuit, a low-power 4th-order Gm-C LPF, and a single-slope ADC. The AC coupling circuit transfers only AC signal while it blocks DC signal level. Considering the bandwidth of the auditory signal, the Gm-C LPF is designed with OTAs adopting floating-gate technique. For the channel-parallel ADC structure, the single-slope ADC is used because it occupies the small silicon area. Experimental results shows that the AC coupling circuit and LPF have the bandwidth of 100 Hz - 6.95 kHz and the ADC has the effective resolution of 7.7 bits. The power consumption per a channel is $12\;{\mu}W$, the power supply is 3.0 V, and the core area is $2.6\;mm\;{\times}\;3.7\;mm$. The proposed analog front-end was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.2
• /
• pp.143-151
• /
• 2013

NAND flash-based SSDs (Solid State Drive) have advantages of fast input/output performance and low power consumption so that they could be widely used as storages on tablet, desktop PC, smart-phone, and server. But, SSD has the disadvantage of wear-leveling due to increase of the number of writes. In order to improve the lifespan of the SSD, a variety of data deduplication techniques have been introduced. General fixed-size splitting method allocates fixed size of chunk without considering locality of data so that it may execute unnecessary chunking and hash key generation, and variable-size splitting method occurs excessive operation since it compares data byte-by-byte for deduplication. This paper proposes adaptive chunking method based on application locality and file name locality of written data in SSD-based server storage. The proposed method split data into 4KB or 64KB chunks adaptively according to application locality and file name locality of duplicated data so that it can reduce the overhead of chunking and hash key generation and prevent duplicated data writing. The experimental results show that the proposed method can enhance write performance, reduce power consumption and operation time compared to existing variable-size splitting method and fixed size splitting method using 4KB.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.10
• /
• pp.1071-1078
• /
• 2014

Recently, information providing service using Big Data is being expanded. Big Data processing technology is actively being academic research to an important issue in the IT industry. In this paper, we analyze a skilled pattern of welder through Big Data analysis or extraction of welding based on R programming. We are going to reduce cost on welding work including weld quality, weld operation time by providing analyzed results non-skilled welder. Welding has a problem that should be invested long time to be a skilled welder. For solving these issues, we apply connection rules algorithms and regression method to much pattern variable for welding pattern analysis of skilled welder. We analyze a pattern of skilled welder according to variable of analyzed rules by analyzing top N rules. In this paper, we confirmed the pattern structure of power consumption rate and wire consumption length through experimental results of analyzed welding pattern analysis.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.9
• /
• pp.1045-1050
• /
• 2008

In this paper presents a CMOS RF receiver for IR-UWB wireless communications is presented. The impulse radio based UWB receiver adopts the non-coherent demodulation that simplifies the receiver architecture and reduces power consumption. The IR-UWB receiver consists of LNA, envelop detector, VGA, and comparator and the receiver including envelope detector, VGA, and comparator is fabricated on a single chip using $0.18{\mu}m$ CMOS technology. The measured sensitivity of IR-UWB receiver is down to -70 dBm and the BER $10^{-3}$, respectively at data rate 1 Mbps. The current consumption of IR-UWB receiver except external LNA is 5 mA at 1.8 V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.6 s.348
• /
• pp.47-52
• /
• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.1
• /
• pp.56-63
• /
• 2008

This paper describes a 12 bit 1GS/s current mode segmented DAC for WCDMA communication. The proposed circuit in this paper employes segmented structure which consists of 4bit binary weighted structure in the LSB and 4bit thermometer decoder structure in the mSB and MSB. The proposed DAC uses delay time compensation circuits in order to suppress performance decline by delay time in segmented structure. The delay time compensation circuit comprises of phase frequency detector, charge pump, and control circuits, so that suppress delay time by binary weighted structure and thermometer decoder structure. The proposed DAC uses CMOS $0.18{\mu}m$ 1-poly 6-metal n-well process, and measured INL/DNL are below ${\pm}0.93LSB/{\pm}0.62LSB$. SFDR is approximately 60dB and SNDR is 51dB at 1MHz input frequency. Single DAC's power consumption is 46.2mW.

• Journal of the Korea Society of Computer and Information
• /
• v.20 no.2
• /
• pp.79-88
• /
• 2015

This paper introduces surveillance equipment "ADS-B", the core subject of traffic control system and study of ADS-B 1090ES ground receiver. The standard is set not only for functional but also its reliability by analyzing international standard documents and existing products. The Bias circuit is designed for less power consumption, low noise and high gain for RF module. The signal processing is capable of overcoming its bad conditions. MCU part is configured with the latest CPU for high speed communication with external parts and SNMP is selected for remote control communication. The performance of developed receiver satisfies national and international standards and its functions are more advanced compared to foreign receivers.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.8
• /
• pp.959-965
• /
• 2019

In this paper, we design a low noise amplifier to support ka-band satellite communication systems using 65-nm RFCMOS process. The proposed low noise amplifier is designed with high-gain mode and low-gain mode, and is designed to control the gain according to the magnitude of the input signal. In order to reduce the power consumption, the supply voltage of the entire circuit is limited to 1 V or less. We proposed the gain control circuit that consists of the inverter structure. The 3D EM simulator is used to reduce the size of the circuit. The size of the designed amplifier including pad is $0.33mm^2$. The fabricated amplifier has a -7 dB gain control range in 3 dB bandwidth and the reflection coefficient is less than -6 dB in high gain mode and less than -15 dB in low gain mode.