• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.55-56
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• 2015

A smart meter is a kind of electronic meters that measures and records consumption of electric energy in intervals of an hour or less and transmits that information to the remote places. AMI provides two-way communication path between utilities and consumers and should be able to support smart grid's new functionalities such as demand-response actions and real time pricing. The main objective of this paper is to provide a new diagnosis method and system for testing of smart meters in AMI neighborhood area network.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.531-536
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• 2021

As artificial intelligence technology advances, it is being applied to various application fields. Artificial intelligence is performing well in the field of image recognition and classification. Chip design specialized in this field is also actively being studied. Artificial intelligence-specific chips are designed to provide optimal performance for the applications. At the design task, memory component optimization is becoming an important issue. In this study, the optimal algorithm for the memory size exploration is presented, and the optimal memory size is becoming as a important factor in providing a proper design that meets the requirements of performance, cost, and power consumption.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.177-180
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• 2011

In practice, it is well known that geographical and/or location based routing is highly effective for wireless sensor network. Here, electing some landmarks on the network and forwarding data based on the landmark is one of the good approaches for a vast sensing field with holes. In the most previous works, landmarks are elected without considering the residual energy on each sensor. In this paper, we propose an Energy aware Landmark Election and Routing (ELER) protocol to establish a stable routing paths and reduce the total power consumption. The proposed protocol makes use of each sensor's energy level on electing the landmarks, which would be utilized to route a packet towards the target region using greedy forwarding method. Our simulation results illustrate that the proposed scheme can significantly reduce the power dissipation and effectively lengthen the lifetime of the network.

• Journal of Sensor Science and Technology
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• v.31 no.3
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• pp.139-144
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• 2022

Advanced tactile sensors are receiving significant attention in various industries such as extended reality, electronic skin, organic user interfaces, and robotics. The capabilities of advanced tactile sensors require a variety of functions, including position sensing, pressure sensing, and material recognition. Moreover, they should comsume less power and be bio-friendly with human contact. Recently, a tactile sensor based on the triboelectrification effect was developed. Triboelectric tactile sensors have the advantages of wide material availability, simple structure, and low manufacturing cost. Because they generate electricity by contact, they have low power consumption compared to conventional tactile sensors such as capacitive and piezoresistive. Furthermore, they have the ability to recognize the contact material as well as execute position and pressure sensing functions using the triboelectrification effect. The aim of this study is to introduce the progress of research on triboelectrification-based tactile sensors with various functions such as position sensing, pressure sensing and contact material recognition.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.4
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• pp.617-624
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• 2023

Recently, miniaturization and low power consumption of electronic products and improved efficiency and power factor improvement have become a matter of great interest. In this paper, an AC-DC converter based on PWM control was designed and made. The AC-DC converter is designed with a structure in which one rectifier circuit and one output voltage control circuit are connected in series. The rectifier circuit is a diode-based single phase full-wave current circuit and the output voltage control circuit is a DC-DC conversion circuit based on PWM control. Arduino was used as the main control device for PWM control, and LCD was configured at the output stage so that the control result could be checked. The error between the output voltage displayed on the oscilloscope and LCD and the target output voltage was confirmed through repeated experiments with the test circuit, and the validity of the proposed design methodology was confirmed by showing an error rate of about 5% based on the oscilloscope measurement value.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.7
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• pp.3066-3079
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• 2016

Recent years have witnessed a dramatic increase in topology research of wireless sensor networks (WSNs) where both energy consumption and survivability need careful consideration. To balance energy consumption and ensure survivability against both random failures and deliberate attacks, we resort to complex network theory and propose an energy-aware preferential attachment (EPA) model to generate a robust topology for WSNs. In the proposed model, by taking the transmission range and energy consumption of the sensor nodes into account, we combine the characters of Erdős -Rényi (ER) model and Barabasi-Albert (BA) model in this new model and introduce tunable coefficients for balancing connectivity, energy consumption, and survivability. The correctness of our theoretic analysis is verified by simulation results. We find that the topology of WSNs built by EPA model is asymptotically power-law and can have different characters in connectivity, energy consumption, and survivability by using different coefficients. This model can significantly improve energy efficiency as well as enhance network survivability by changing coefficients according to the requirement of the real environment where WSNs deployed and therefore lead to a crucial improvement of network performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.69-76
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• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.5
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• pp.423-432
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• 2023

With the increasing demand for mobile devices featuring multi-touch operation, extensive research is being conducted on touch screen panel (TSP) Readout ICs (ROICs) that should possess low power consumption, compact chip size, and immunity to external noise. Therefore, this paper discusses capacitive touch sensors and their readout circuits, and it introduces research trends in various circuit designs that are robust against external noise sources. The recent state-of-the-art TSP ROICs have primarily focused on minimizing the impact of parasitic capacitance (Cp) caused by thin panel thickness. The large Cp can be effectively compensated using an area-efficient current compensator and Current Conveyor (CC), while a display noise reduction scheme utilizing a noise-antenna (NA) electrode significantly improves the signal-to-noise ratio (SNR). Based on these achievements, it is expected that future TSP ROICs will be capable of stable operation with thinner and flexible Touch Screen Panels (TSPs).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.