• Journal of IKEEE
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• v.15 no.4
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• pp.261-266
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• 2011

In this paper, new efficient lighting control system for light devices is proposed to reduce power consumption and increases LED life-cycle and heat efficiency of LED lighting module. The new proposed lighting control system for light devices divides into 4 stages according to the illuminance surrounding by measuring illuminance and apply to automatic pattern lighting algorithm. And via level check will be light up for set time by applying intersection lighting algorithm of magic square pattern forming a fully symmetrical. Experimental analysis results, shows heating value and power consumption reduced to maximum 30 percent and lifetime of LED improved to maximum 60 percent in comparison with previous lighting system so applying system to LED streetlight, stable and high energy efficiency can be acquired.

• Journal of IKEEE
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• v.28 no.2
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• pp.228-233
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• 2024

Due to the recent COVID-19 pandemic, various methods have been devised to prevent infections caused by physical contact. Among them, a non-contact button was developed to prevent infections in elevators, where many contacts occur in daily life. In this study, an active shield type capacitance sensor is used to detect changes in capacitance when a finger approaches. There is no static power consumption, and the relatively expensive ADC and MCU are reduced to one by sensing buttons every time using analog switches. In addition to the elevator buttons, this technology is expected to replace push-type buttons that many people contact in everyday life.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.6
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• pp.47-56
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• 2010

HDD-based RAIDs have been used in high-capacity storage systems for traditional data server. However, their data reliability are relatively low and they consume lots of power since hard disk drive is weak on shock and its power consumption is high due to frequent spindle motor operation. Therefore, this paper presents new SSD based RAID system architecture using various erasure codes. The proposed methode applys Reed-Solomon, EVENODD, and Liberation coding schemes onto file system level and device driver level, respectively. Besides, it uses data allocation method to minimize the side effect of reducing the lifespan of SSD. Detail experimental results show that Liberation code increase wear-leveling rates of SSD based RAID-6 more than other codes. The SSD based RAID system applying erasure codes at the device driver level shows better performance than that at the file system level. I/O performance of RAID-6 system using SSD is 4.5%~8.5% higher than that of using HDD and the power consumption of the RAID system using SSD is 18%~40% less than that of using HDD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.6-7
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• 2008

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450V power MOSFET devices by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5\times10^{14}cm^{-3}$, size of $600{\mu}m^2$ with 4.5 $\Omega$, and off-state leakage current below 50 ${\mu}A$. We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods is meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.437-441
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• 2006

Wireless sensor network consists of sensor nodes which are disseminated closely to each other to collect informations for the various requests of a sensor application applied for sensing phenomenons in real world. Each sensor node delivers sensing informations to an end user by conducting cooperative works such as processing and communicating between sensor nodes. In general, the power supply of a sensor node is depends on a battery so that the power consumption of a sensor node decides the entire life time of a sensor network. To resolve the problem, optimal routing algorithm can be used for prolong the entire life time of a sensor network based on the information on the energy level of each sensor node. In this paper, different from the existing Directed Diffusion and SPTN method, we presents a data dissemination protocol based on lower-power consumption that effectively maximizes the whole life time of a sensor network using the informations on the energy level of a sensor node and shortest-path hops. With the proposed method, a data transfer path is established using the informations on the energy levels and hops, and the collected sensing information from neighboring nodes in the event-occurring area is merged with others and delivered to users through the shortest path.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.5
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• pp.779-785
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• 2015

Recently, home energy management system (HEMS) for power consumption reduction has been widely used and studied. The HEMS performs electric power consumption control for the indoor electric device connected to the HEMS. However, a traditional HEMS is used for passive control method using some particular power saving devices. Disadvantages with this traditional HEMS is that these power saving devices should be newly installed to build HEMS environment instead of existing home appliances. Therefore, an HEMS, which performs with existing home appliances, is needed to prevent additional expenses due to the purchase of state-of-the-art devices. In this paper, an intelligent inference algorithm for EMS at home for non-power saving electronic equipment, called legacy devices, is proposed. The algorithm is based on the adaptive network fuzzy inference system (ANFIS) and has a subsystem that notifies retraining schedule to the ANFIS to increase the inference performance. This paper discusses the overview and the architecture of the system, especially in terms of the retraining schedule. In addition, the comparison results show that the proposed algorithm is more accurate than the classic ANFIS-based EMS system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.918-922
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• 2006

Chalcogenide Phase change memory has the high performance necessary for next-generation memory, because it is a nonvolatile memory with high programming speed, low programming voltage, high sensing margin, low power consumption and long cycle duration. To minimize the power consumption and the program voltage, the new composition material which shows the better phase-change properties than conventional $Ge_2Sb_2Te_5$ device has to be needed by accurate material engineering. In the present work, we investigate the basic thermal and the electrical properties due to phase-change compared with chalcogenide-based new composition $Ge_1Se_1Te_2$ material thin film and convetional $Ge_2Sb_2Te_5$ PRAM thin film. The fabricated new composition $Ge_1Se_1Te_2$ thin film exhibited a successful switching between an amorphous and a crystalline phase by applying a 950 ns -6.2 V set pulse and a 90 ns -8.2 V reset pulse. It is expected that the new composition $Ge_1Se_1Te_2$ material thin film device will be possible to applicable to overcome the Set/Reset problem for the nonvolatile memory device element of PRAM instead of conventional $Ge_2Sb_2Te_5$ device.