• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.563-569
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• 2015

For some low-frequency applications such as power-related circuits, NEM relays have been known to show better performance than MOSFETs. For example, in a step-down charge pump circuit, the NEM relays showed much smaller layout area and better energy efficiency than MOSFETs. However, severe process variations of NEM relays hinder them from being widely used in various low-frequency applications. To mitigate the process-variation problems of NEM relays, in this paper, a new NEM-relay charge pump circuit with the self-adjustment is proposed. By self-adjusting a pulse amplitude voltage according to process variations, the power consumption can be saved by 4.6%, compared to the conventional scheme without the self-adjustment. This power saving can also be helpful in improving the power efficiency of the proposed scheme. From the circuit simulation of NEM-relay charge pump circuit, the efficiency of the proposed scheme is improved better by 4.1% than the conventional.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.92-97
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• 2009

Low power consumption is crucial for medical implantable devices. A low-power 4th-order band-pass Gm-C filter with distributed gain stage for the sensing stage of the implantable cardiac pacemaker is proposed. For the implementation of large-time constants, a floating-gate operational transconductance amplifier with current division is employed. Experimental results for the filter have shown a SFDR of 50 dB. The power consumption is below $1.8{\mu}W$, the power supply is 1.5 V, and the core area is $2.4\;mm{\times}1.3\;mm$. The filter was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.73-81
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• 2000

This paper presents the design and simulation of a power and area efficient interpolation FIR filter with partitioned look up table (LUT) structure. Using the symmetry of the filters coefficients and the contents of the LUT, the area of the proposed filter is minimized. The two filters share the partitioned LUT and activate the LUT selectively to realize the low power operation. The proposed filter has been designed in a 5.0 Volts 0.6${\mu}m$ CMOS technology. Power consumption results have been obtained from Powermill simulations. Experimental results suggest that the proposed filter reduces both the power consumption by 28% and simultaneously the gate area by 5% simultaneously compared to the previously proposed filters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.327-328
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• 2008

In this study, it was studied about the improved road light design for drivers and pedestrians using ray- or reverse ray-tracing method. Many of conventional road lights are not suitable for drivers and pedestrians because it has some serious problems such as glare effect or randomicity of illuminated areas. It was oriented from customary design method which was pointed at simple target such as luminance or electrical power. But it was not truth any more that the high luminance or electrical power consumption mean more bright and good road light. We studied ray-tracing method for road light reflector design to get the several goals. It means that good road light has easy for drivers and pedestrians eyes and illuminating objects on the road clearly. So, we set the design targets such as uniformity on the road area per one road light, shading angles and continuous luminance uniformity on the long distance road. We designed ideal road light conditions using ray-tracing method. We set the height of drivers and pedestrians eyes and calculated design guideline to make above design targets. Then we designed road light reflector using reverse ray-tracing method. And we achieved same luminance on the road almost half power consumption because we reduced loss of light. We achieved ideal design guide as 75 degrees of shading angles and 0.5 of luminance uniformity on the road area. Finally, we suggested reflector design for 250 watts power consumption CDM light source.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Journal of IKEEE
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• v.23 no.1
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• pp.120-126
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• 2019

Recently, accurate prediction of power consumption based on machine learning techniques in Internet of Energy (IoE) has been actively studied using the large amount of electricity data acquired from advanced metering infrastructure (AMI). In this paper, we propose a deep learning model based on Gated Recurrent Unit (GRU) as an artificial intelligence (AI) network that can effectively perform pattern recognition of time series data such as the power consumption, and analyze performance of the prediction based on real household power usage data. In the performance analysis, performance comparison between the proposed GRU-based learning model and the conventional learning model of Long Short Term Memory (LSTM) is described. In the simulation results, mean squared error (MSE), mean absolute error (MAE), forecast skill score, normalized root mean square error (RMSE), and normalized mean bias error (NMBE) are used as performance evaluation indexes, and we confirm that the performance of the prediction of the proposed GRU-based learning model is greatly improved.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.155-160
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• 2019

In this paper, we propose an efficient grid-independent ESS control system through the control of renewable energy and agricultural ICT by utilizing the prediction of energy production and consumption. The proposed system is an integrated management system that can perform maintenance and monitoring by visualizing the accurate phase and data of power system. It can automatically cope, collect, process, and control the data. Also, it can analyze the power generation of solar power generation, consumption pattern of installed facilities, and operation trend of facilities. Further, it can predict the consumption of energy production and present the optimal energy management method by using the OpenAPI of the Korea Meteorological Administration, thereby reducing unnecessary energy consumption and operating cost.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.889-897
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• 2014

With the development of wireless communication and sensor technology, sensor network applications in various fields have been applied. To minimize the power consumption of sensors in sensor network is one of the important factors in oder to extend the system life. The power consumption of each sensor within sensor network can be different depending on the communication method between head(sink) node and its node. In this paper, we propose a new hierarchical communication method to minimize the power consumption of each sensor. The proposed method divides the area of sensor network into four areas using divide-and-conquer method and selects the nearest node to head node in each area as a child node of the node. Next the hierarchical tree in the same way is constructed recursively until each area is no longer divided. Each sensor can communicate to head node using this hierarchical tree. The proposed results were compared with the previous methods through simulation, and showed excellent results in the energy efficiency of sensor network.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.32-33
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• 2006

As next generation nonvolatile memory, chalcogenide-based phase change memory can substitute for a conventional flash memory from its high performance. Also, fast writing speed, low writing voltage, high sensing margin, low power consumption and repetition reliability over $10^{15}$ cycle shows its possibility. At our laboratory, we invented ${Ge_1}{Se_1}{Te_2}$ material to alternate with conventional ${Ge_2}{Sb_2}{Te_5}$ for improve its ability. We respect the ${Ge_1}{Se_1}{Te_2}$ material can be a solution for high power consumption problem and long time at 'set' performance. A conductivity experiment from variable temperature was performed to see reliability of repetition at read and write performance. Compare with conventional ${Ge_2}{Sb_2}{Te_5}$ material, these two materials are used as complex compound to get the finest parameter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.52-58
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• 2009

A low voltage, low power delta-sigma modulator is proposed for cardiac pacemaker applications. A cascade of delta-sigma modulator stages that employ a feedforward topology has been used to implement a high-resolution oversampling ADC under the low supply. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption. An experimental prototype of the proposed circuit has been implemented in a $0.35-{\mu}m$ CMOS process, and it achieves 61-dB SNDR, 63-dB SNR, and 65-dB DR for a 120-Hz signal bandwidth at 7.6-kHz sampling frequency. The power consumption is only 280 nW at 1-V power supply.