• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.9
• /
• pp.1493-1496
• /
• 2016

This paper proposes a system for reducing the standby power consumption in using the consumer electronic devices such as a television, a home theater, a set-top box, or a DVD player. The system is consisted of a flyback converter, monitoring circuits, a relay and a micro-processor. The proposed system can reduce the standby power consumption by disconnecting the AC input and the consumer devices can be turned on with a remote control. The proposed standby power system consumes the low power to receive the infrared signal from the remote controller. Furthermore, a electronic double layer capacitor is used to store the energy with high efficiency. The proposed power system can operate the 플라이백 converter to charge the electronic double layer capacitor and connect the AC input to the consumer electronic devices. The proposed power circuit can reduce the standby power consumption in AV devices without increasing the cost. The prototype is implemented to verify the system with the commercialized products.

• Journal of Power Electronics
• /
• v.13 no.3
• /
• pp.362-368
• /
• 2013

Commercial home appliances using remotely controlled systems consume electric power while in standby mode to prepare for receiving a remote turn-on signal. The proposed power system can significantly reduce standby power consumption without increasing cost. Furthermore, since a Electronic Double Layer Capacitor (EDLC) is used as an auxiliary power storage element, the life cycle is longer and system reliability can be better than with existing approaches. When the energy of the EDLC is not sufficient for turning on the appliance, the power system charges the EDLC without affecting the main system. The proposed power system is verified with a commercial LCD TV and a 3.93mW standby consumption is obtained. This standby consumption can be regarded as zero standby equipment according to the IEC-62031 standard.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.222-225
• /
• 2006

A custom-made display driver for an electronic paper is presented, which has high-voltage multilevel output capability and extremely low power consumption. An original level-shifter circuit can effectively reduce the power consumption and the chip area. This driver was implemented to a Quick-Response Liquid Powder Display (QR-LPD) and the image quality and power consumption was estimated.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.9 no.2
• /
• pp.75-80
• /
• 2014

Energy consumption of sensor nodes is minimized because it has limited energy generator in wireless sensor network. Electronic shelf label system is one of application fields using wireless sensor networks. Battery size of small apparatus for displaying price is restricted. Therefore its current consumption have to be minimized. Furthermore the method for minimization of peak current would be considered because life cycle of coin battery used to display or RF is vulnerable to intensity of drain current. In this paper, we analyze current consumption pattern of low-power electronic shelf label system. Then we propose the method for minimization of current consumption by modification of software and hardware. Current consumption of the system using proposed method are approximately 15 to 20 percent lower than existing system and the life cycle of the system is approximately 10 percent higher than existing system.

• Journal of Sensor Science and Technology
• /
• v.30 no.2
• /
• pp.82-87
• /
• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.257-263
• /
• 2002

Test scheduling of SoC becomes more important because it is one of the prime methods to minimize the testing time under limited power consumption of SoCs. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoCs is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position to minimize the idle test time of test resources.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.6
• /
• pp.293-302
• /
• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.4
• /
• pp.369-375
• /
• 2023

In this paper, we compared and analyzed the power load patterns of dormitory buildings and office buildings to use them as basic data (demand analysis and capacity design) for the design and operation of microgrids for multi-use facilities, and the following conclusions were got. During the daytime on regular weekdays, the power consumption load pattern of office buildings was relatively large at 264.0~332.3 kWh, and during the evening hours, the power consumption load pattern of dormitory buildings was relatively large at 233.0~258.3 kWh. In the case of vacation, during the daytime on weekdays, the power consumption load pattern of office buildings was relatively large at 279.1~407.4 kWh, and in the evening, the power consumption load pattern of dormitory buildings was relatively high at 280.1~394.1 kWh. During the daytime on regular weekends, the power consumption of dormitory-type buildings was relatively high at 133.5~201.6 kWh, and it was found that the power consumption of dormitory-type buildings appeared relatively high at 187.5~252.1 kWh. During a vacation in the daytime on weekends, the power consumption of dormitory-type buildings was found to be 186.5 kWh~ and 218.6 kWh. The increase in power consumption during a vacation (December-February) compared to normal (April-June) was thought to be due to an increase in electricity demand, and the reason for the higher power consumption in dormitory buildings during the vacation was due to reduced working hours in office buildings.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.47 no.1
• /
• pp.30-40
• /
• 2010

The hard disk is one of the most frequently used storage in IPTV sep-top box. It has large storage capacity and provides fast I/O speed compared to its price whereas it causes high power consumption due to mechanical characteristics of spindle motor. In order to play streaming data in the set-top box, spindle motor of hard disk keeps active mode and it causes high power consumption. In this paper, We propose an offset-buffering and multi-mode spin-down method to reduce power consumption for streaming data playback. The offset-buffering inspects the user's viewing pattern and performs buffering based on the analysis of viewing pattern. So, it can maintain the status of spindle motor as idle mode for long time. Besides, it can reduce power consumption by spinning down according to offset-buffer size. The experimental result shows that proposed offset-buffering and multi mode spin-down method is about 28.3% and 12.5% lower than the full-Buffering method in terms of the power consumption and spin-down frequency, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.2
• /
• pp.159-165
• /
• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.