• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.194-198
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• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.347-350
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• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• Transactions on Electrical and Electronic Materials
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• 제17권6호
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• 제어로봇시스템학회논문지
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• 제3권1호
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• pp.101-108
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• 1997

The initial token value required to the optimal performance of discrete event systems can be decided by Sum of Delay Time and Synchronic Time ratio, which are new synchronic variables in Timed Place Petri Nets. For the system consisting of two Live-and-Bounded circuits(LB-circuits) fused in common Transition-Transition-Path or common Place-Place-Path, we prove that the Synchronic Time Ratio is the initial token ratio between two LB-circuits to optimally perform system functions. These results are generalized and formulated as a theorem. The initial tokens of a specific place can imply shared resources. Using the theorem, we can decide the minimum number of the shared resources to obtain the optimal performance, and minimize the idling time of resources. As an example, an automated assembly system is modeled by Timed Place Petri Net, and the initial tokens to achieve the optimal system performance are identified. All the values are verified by simulation.

• 한국전기전자재료학회논문지
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• 제31권4호
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• pp.261-266
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• 2018

When the clamp meter approaches the electric path where current is flowing, leakage current can be measured at a distance from the electric current because the induced current increases as the magnitude of the current increases and approaches nearer to the electric path. Therefore, measurements were carried out from a distance to avoid this effect. In addition, the measured values differ depending on the location of the power line that penetrates the ZCT of the clamp meter, thus measurements were performed at a location where this effect was minimized. The fraction of compliant branch circuits, whose leakage current was lower than 1.00 mA, was found to be 69.0% out of the total of 439 branch circuits, while the percentage of compliant branch circuits having an insulation resistance higher than $0.20M{\Omega}$ was found to be 93.2%. The reason why the percentage of compliant branch circuits with low leakage current was low might be due to the inclusion of capacitive leakage current in the total measured leakage current.

• 공학교육연구
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• 제2권1호
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• pp.10-16
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• 1999

본 논문에서는 인터넷을 이용한 디지탈 논리회로 설계 및 모의실험실습을 위한 교육용 소프트웨어 패키지(DVLab)를 개발하였다. 개발된 패키지는 디지탈 조합/순차회로는 물론 마이크로콘트롤러 응용회로까지 설계하고 시뮬레이션할 수 있는 모듈, 브레드보드 시뮬레이터 모듈, 실험항목별 이론 강의를 위한 모듈, 보고서 작성 및 보고서 자동검사 모듈 등을 포함하고 있다. 개발된 모든 모듈들은 독립적인 응용 프로그램으로 뿐만 아니라 인터넷을 이용한 사용이 가능하며, 특히 시뮬레이터 모듈의 경우 실시간 클럭 제공, 설계회로도 상에서 직접 소자의 출력값 확인, 논리값 변화 기록 기능, 설계회로 복사 방지 기능, 다양한 논리회로 소자뿐만 아니라 LED, buzzer등과 같은 시각적, 청각적 소자 제공 등의 특징을 가진다. 또한 개발된 교육용 패키지를 이용한 디지탈 논리회로 실험실습 과목의 학습 모형을 제시하였다.

• 한국신뢰성학회지:신뢰성응용연구
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• 제12권3호
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• pp.153-163
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• 2012

Recently, as a electronic components are becoming more high-density, so that electronic circuits have smaller pitches between the leads and are more vulnerable to insulation failure. And the reliability of electric insulation has become an ever important issue as device contact pitches and print patterns shrink. Ion migration occurs in highly humid environment as voltage is applied to an installed print circuit. Under highly humid and voltage applied circumstances, electronic components respond to applied voltages by electrochemical ionization of metals, and a conducting filament forms between the anode and cathode across a nonmetallic medium. This leads to short-circuit failure of the electronic component. In thesis, we study acceleration test of ion migration in FR-4 PCB plated with Sn. Voltage applied test of FR-4 PCB circuits plated with Sn was tested in the temperature and humidity environments. As a result of this test, equation of acceleration model was derived.

• ETRI Journal
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• 제26권6호
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.