• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.4
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• pp.388-393
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• 2019

As a fiiting method to data with outliers, RANSAC(RANdom SAmple Consensus) based algorithm is widely used in fitting of line, circle, ellipse, etc. CUDA is currently most widely used GPU with massive parallel processing capability. This paper proposes an efficient CUDA implementation of multiple planes fitting using RANSAC with 3d points data, of which one set of 3d points is used for one plane fitting. The performance of the proposed algorithm is demonstrated compared with CPU implementation using both artificially generated data and real 3d heights data of a PCB. The speed-up of the algorithm over CPU seems to be higher in data with lower inlier ratio, more planes to fit, and more points per plane fitting. This method can be easily applied to a wide variety of other fitting applications.

• Journal of Information Processing Systems
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• v.2 no.1
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• pp.58-65
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• 2006

Accurate and efficient monitoring of dynamically changing environments is one of the most important requirements for ubiquitous network environments. Ubiquitous computing provides intelligent environments which are aware of spatial conditions and can provide timely and useful information to users or devices. Also, the growth of embedded systems and wireless communication technology has made it possible for sensor network environments to develop on a large scale and at low-cost. In this paper, we present the design and implementation of a monitoring system that collects, analyzes, and controls the status information of each sensor, following sensor data extracted from each sensor node. The monitoring system adopts Web technology for the implementation of a simple but efficient user interface that allows an operator to visualize any of the processes, elements, or related information in a convenient graphic form.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.225-228
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• 2008

In this paper, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features: composite field arithmetic SubByte, efficient MixColumn transformation, and On-the-Fly Key-Scheduling for fully pipelined architecture. By pipelining the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the On-the-Fly key scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.

• Journal of Korea Multimedia Society
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• v.19 no.2
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• pp.122-127
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• 2016

This paper propose implementation method of SoC system for efficient depth image segmentation. SoC systems are combined platform in the form of the Software and Hardware IP. In order to perform effectively, the user to determine the operation of the configuration of each part. In this paper, we implemented a segmentation of depth images taken by the infrared sensor at APU of SoC system. The proposed method efficiently implements high performance and low power in SoC system. Proposed method that using software parts of SoC system is capable to use at several depth image processing systems.

• ETRI Journal
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• v.32 no.2
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• pp.222-229
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• 2010

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

• ETRI Journal
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• v.35 no.1
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• pp.18-26
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• 2013

This paper proposes an efficient bandwidth utilization (EBU) algorithm that utilizes the unused bandwidth in dynamic bandwidth allocation (DBA) of a 10-gigabit-capable passive optical network (XGPON). In EBU, an available byte counter of a queue can be negative and the unused remainder of an available byte counter can be utilized by the other queues. In addition, EBU uses a novel polling scheme to collect the requests of queues as soon as possible. We show through analysis and simulations that EBU improves performance compared to that achieved with existing methods. In addition, we describe the hardware implementation of EBU. Finally we show the test results of the hardware implementation of EBU.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.119-122
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• 2000

Recently, many complex DSP (Digital Signal Processing) algorithms have being realized on RISC CPU due to good compilation, low power consumption and large memory space. But, real-time implementation of multiple DSP algorithms on RISC requires the minimum and efficient memory usage and the lower occupancy of CPU. In this thesis, the original floating-point code of MPEG-1 audio decoder is converted to the fixed-point code and then optimized to the efficient assembly code in time-consuming function in accord with RISC feature. Finally, compared with floating-point and fixed-point, about 30 and 3 times speed enhancements are achieved respectively. And 3~4 times memory spaces are spared.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.10
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• pp.1338-1346
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• 1995

In this paper, we suggest the implementation of a DGPS system using two low cost commercial C/A code GPS modules and modems and its efficient operational techniques to provide DGPS service which guarantees the position accuracy of better than 10 meters for more users. The proposed DGPS system can be implemented easil at low cost because it needs a GPS module and a modem for each reference station and user. The reference station makes plans of the receiving schedule from the satellite set at each period and then provides the correction data for various satellite sets in a period. The main contribution of this paper is that users can utilize the correction data continuously and efficiently through the recursive least squares lattice filtering method. Experimental results show the position accuracy of better than 10 meters using the suggested DGPS system in almost real time.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.443-445
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• 2002

In this paper, we present a novel efficient semaphore implementation scheme which diminishes completion time of high priority tasks and improves reliability of a system. The real-time system is constrained to complete their tasks in time. Especially, the task of a hard real-time system must meet its deadline under unfavorable conditions. In this paper, the number and sort of the locked semaphores, when an event occurred, decide whether the context switch should occur or not, so higher priority tasks diminish in their completion time. The experimental results show that the proposed method gives performance improvements in finish time of high priority tasks of about 11% over the Zuberi.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.183-189
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• 2015

In this paper, we propose an efficient implementation method that current-voltage sourcing and measuring for LED using (+) single power. this method has the advantage of reducing the error of the circuit and calibration of system, and also improving the complexity of hardware than the method of using a (+)(-) current or voltage sourcing and measuring.